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390 Views
Registered: ‎04-01-2019

How to identify MSI interrupt generated or not?

I wanted to generate MSI interrupt from @EP device. But wondering after doing all the required configurations in order to generate MSI interrupt, how can I check if the interrupt generated or not?

Here are the configurations I have done:

@EP

  • Enable MSI capability
  • Set MSI Address
  • Set MSI Data
  • Enable ‘Bust Master Enable’ bit.

@RP

  • Enable ‘Bust Master Enable’ bit.
  • Enable ‘Memory Space Access’

So doing above steps will generate MSI interrupt upon any error occured?

If yes, how I will verify if interrupt generated or not?

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5 Replies
Xilinx Employee
Xilinx Employee
344 Views
Registered: ‎07-26-2012

Re: How to identify MSI interrupt generated or not?

Can you let me know what kind of IP and device are you using?

 

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330 Views
Registered: ‎04-01-2019

Re: How to identify MSI interrupt generated or not?

I have an EP (PCIe Compliance Exerciser card) is connected over Server PCIe slot.

I have full register controls at both the ends. I'm wondering how can I generate MSI interrupt?

Is it possible from EP side or RP can also generate?

And how to generate + how to identify if MSI interrupt generated or not?

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Xilinx Employee
Xilinx Employee
321 Views
Registered: ‎07-26-2012

Re: How to identify MSI interrupt generated or not?

I'm sorry but I'm a little confused. Is this question for a case where the Exerciser card plugs into the slot of the Server? Is FPGA not used?

If so, you should be able to issue an MSI from the  exerciser card as an EP. For more information, please refer to the Exerciser card manual.

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311 Views
Registered: ‎04-01-2019

Re: How to identify MSI interrupt generated or not?

Actually FPGA is used. I mean to say 'Exerciser' here is that its a customised FPGA PCIe card which we are using for our validation purposes. May be if I can get the steps, how we can generate MSI, that would be very helpful. 

For generating MSI, do I need to map BAR address at any point?

Or MSI address of EP should match to RP MSI address?

I'm not getting clarity on what basis MSI address should be mapped?

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Xilinx Employee
Xilinx Employee
282 Views
Registered: ‎07-26-2012

Re: How to identify MSI interrupt generated or not?

MSI Message Address and MSI Message Data are writtern by software on the host system. FPGA as an EP does not need to set the values.