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Voyager
Voyager
481 Views
Registered: ‎05-14-2017

How to incorporate multiple IP PCIe and DDR3 into design

I am using multiple IP, the PCIe and DDR3 and each one I started with the Xilinx  Design Example IP in different project.

 

From one of my Project where the  PCIe Design Example resides, I have created my design using the PCIe core.

How would I bring in the DDR3 Design Example IP into this project?

 

I assume there must be a many files that I need from the DDR3 Design Example IP project and not sure what is the appropriate way to do this.

 

Regard

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Moderator
Moderator
383 Views
Registered: ‎02-16-2010

Re: How to incorporate multiple IP PCIe and DDR3 into design

Are you using PCIexpress hardblock IP (or) XDMA (or) AXI PCIe?

If you are using XDMA, please refer to the video shown below.
https://www.youtube.com/watch?v=TzzzM97L4HI

AXI PCI Express MIG Subsystem Built in IPI:
https://www.youtube.com/watch?v=0KnvW_6Bgu0
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