04-06-2021 02:57 PM
I have a card based on a zu28/zu48 RFSOC with a PCIe interface implemented in the PL-side of the device using the DMA/Bridge Subsystem for PCI Express IP. The card is connected to a PC motherboard using a PCIe cable. All of this works but the system seems to be susceptible to ESD, so I want to verify the serial links margins. For this I am trying to use IBERT instantiated via a configuration option in the DMA/Bridge Subsystem. I have replaced the motherboard with a PCIe loopback board by Kaya Instruments. The problem is that the eye diagrams I am getting with this setup look like complete rubbish. Does this setup even make sense or it is not going to work without the PCIe link training? I suspect that missing the training is critical but I don't know how to set up a test with the training.
Is there an appnote explaining how to use IBERT for PCIe?
04-06-2021 06:05 PM
Yes, it is expected if the link is down. can you try to use IBERT?
04-14-2021 11:36 AM
Sorry for the delay. I got IBERT working but I am not sure if what I am doing makes sense. Here's what I did:
At the step 3 above I've noticed that the wizard has configured the differential swing and emphasis mode for PCIe Gen1/Gen2, which is wrong for the speed I chose. On the other hand I guess this is supposed to be an initial setting in PCIe before the link training has taken place. Since in my test no PCIe link training is taking place should I configure the wizard differently?
Is there a way to use IBERT in a sort of snooping mode with a real application? I have a design, which seems unreliable, especially when used with a PCIe riser cable and I want to somehow verify that the physical layer is compliant to the spec. What's the best and easiest way of reaching this goal?