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mmatusov
Voyager
Voyager
286 Views
Registered: ‎02-17-2009

How to use IBERT with DMA/Bridge Subsystem for PCI Express?

I have a card based on a zu28/zu48 RFSOC with a PCIe interface implemented in the PL-side of the device using the DMA/Bridge Subsystem for PCI Express IP. The card is connected to a PC motherboard using a PCIe cable. All of this works but the system seems to be susceptible to ESD, so I want to verify the serial links margins. For this I am trying to use IBERT instantiated via a configuration option in the DMA/Bridge Subsystem. I have replaced the motherboard with a PCIe loopback board by Kaya Instruments. The problem is that the eye diagrams I am getting with this setup look like complete rubbish. Does this setup even make sense or it is not going to work without the PCIe link training? I suspect that missing the training is critical but I don't know how to set up a test with the training.

Is there an appnote explaining how to use IBERT for PCIe?

Thanks,
/Mikhail

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simon
Xilinx Employee
Xilinx Employee
264 Views
Registered: ‎08-25-2010

Hi @mmatusov 

Yes, it is expected if the link is down. can you try to use IBERT?

https://www.xilinx.com/support/documentation/ip_documentation/ibert_ultrascale_gty/v1_3/pg196-ibert-ultrascale-gty.pdf

Thanks
Simon
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mmatusov
Voyager
Voyager
184 Views
Registered: ‎02-17-2009

Hi @simon 

Sorry for the delay. I got IBERT working but I am not sure if what I am doing makes sense. Here's what I did:

  1. I created a simple design with an xdma core (DMA/Bridge Susbsystem for PCI Express) and configured the core for 8Gb/s;
  2. I created another blank design and added to it the UltraScale FPGAs Transceivers Wizard core that was created for me in the first design;
  3. I right clicked on the transceivers wizard source file and opened an example design for it. But before that I made sure that the physical resources have been correctly assigned in the core to match my board;
  4. I made a few small changes to the top level Verilog file and the constraints file in the example design to make it work on my target board, implemented the design and loaded the bitstream;
  5. At this point I was able to open IBERT and run scans and sweeps on individual links. However, I am not sure if the scans are performed with the correct settings. 

At the step 3 above I've noticed that the wizard has configured the differential swing and emphasis mode for PCIe Gen1/Gen2, which is wrong for the speed I chose. On the other hand I guess this is supposed to be an initial setting in PCIe before the link training has taken place. Since in my test no PCIe link training is taking place should I configure the wizard differently?

Is there a way to use IBERT in a sort of snooping mode with a real application? I have a design, which seems unreliable, especially when used with a PCIe riser cable and I want to somehow verify that the physical layer is compliant to the spec. What's the best and easiest way of reaching this goal?

Thanks,
/Mikhail

 

 

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mmatusov
Voyager
Voyager
169 Views
Registered: ‎02-17-2009

Here are screenshots of some of the scans:

Screenshot - 14-Apr-2021 , 4_54_14 PM.pngScreenshot - 14-Apr-2021 , 4_55_25 PM.pngScreenshot - 14-Apr-2021 , 4_55_50 PM.pngScreenshot - 14-Apr-2021 , 4_56_20 PM.png

I don't understand how is the last one even possible.

Thanks,
/Mikhail

 

 

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