cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
yongcun_ding
Observer
Observer
650 Views
Registered: ‎09-10-2019

How to use the PCIe XDMA ip core to achieve two-way communication with the PC? That is, how does fpga actively upload data to the host?

How to use the PCIe XDMA ip core to achieve two-way communication with the PC? That is, how does fpga actively upload data to the host?
0 Kudos
5 Replies
aforencich
Explorer
Explorer
593 Views
Registered: ‎08-14-2013

As in, you just want to move data from the FPGA to the host, or you want the FPGA to initiate and control the movement of data from the FPGA to the host? The XDMA core supports the first in its default configuration - just have the core read from a streaming input or memory region via AXI. The second requires using the descriptor bypass interface and a lot of custom logic to coordinate with the driver and generate the transfer requests.
0 Kudos
yongcun_ding
Observer
Observer
567 Views
Registered: ‎09-10-2019

Thank you very much for replying to this question. What I want to achieve is the second method of communication. I have now read the manual pg195 and learned some about the descriptor bypass interface, but how to do it is not clear. Is there any more detailed introduction or information in this regard? Thank you .

0 Kudos
aforencich
Explorer
Explorer
562 Views
Registered: ‎08-14-2013

Not sure. I have only read over some of the XDMA core documentation, I have not used the core myself. I had a need for the same feature, but determined that using the XDMA core was too high risk so I ended up writing my own DMA engine.
0 Kudos
yongcun_ding
Observer
Observer
487 Views
Registered: ‎09-10-2019

When I use the XDMA IP core, the descriptor bypass interface is turned on, and there is no problem during simulation, but when debugging with the host, I do not know the destination address of the host, how can you solve this problem. It would be great if you could provide me with your project
0 Kudos
aforencich
Explorer
Explorer
443 Views
Registered: ‎08-14-2013

The code for the DMA data mover components is here: https://github.com/alexforencich/verilog-pcie and the NIC that uses it is here: https://github.com/ucsdsysnet/corundum

The descriptor handling and queue management components are how the NIC design knows the addresses in host memory.  For each queue, there is a DMA-accessible ring buffer in host memory.  The driver allocates these and writes the physical addresses into the queue management logic on the NIC.  Then, when the host wants to send a packet, the driver gets a DMA mapping for the packet, writes the physical address and length into a descriptor in the descriptor ring, and informs the NIC that a descriptor was enqueued.  Then the NIC can issue a DMA read for the descriptor, then a DMA read for the packet data. 

0 Kudos