07-28-2021 09:37 AM
You don't mention what FPGA family you are designing with. Assuming US/US+ there is the "PCI Express Integrated Block". This is lower level block without any AXI support and you'd have to manage all the PCIe TLP response yourself.
07-29-2021 01:17 AM
Thanks. You are right. I am using XCU118. I use MATLAB as AXI master. Previously I used it over JTAG for a long time. Now I am planning to switch to the PCIe for better read write speed. This is their design:
PCI Express MATLAB as AXI Master - MATLAB & Simulink (mathworks.com)
That's why I was wondering if I need XDMA or just use the AXI master IP as I did before with JTAG (Access FPGA External Memory Using MATLAB as AXI Master - MATLAB & Simulink Example (mathworks.com)).