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Kaiyang
Visitor
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Registered: ‎06-06-2021

KU3P+ Tandem PCIE and 64bits DDR4 controller

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We want to use XCKU3P-L1SFVB784I4813 to make a PCIe 3.0  x8 card.

There are only four HP banks, bank 64,bank65,bank66,bank67.

We need a 64bits DDR4 controller. As PG150 saids,  bank skip is not allowed.

I want to put 64bit DDR4 controller into bank65,bank66,bank67.

We use master SPI x4 to load FPGA bitsteams.

We have to load FPGA bitstreams  in 100ms to meet PCIe3.0 specification. So we prepare to use Tandem PCIE.

But on PG213,there's another limit,as picture showen,

Kaiyang_0-1623029937545.png

I want to make sure wheather we can use  Tandem PCIE and 64bits DDR4 controller together on XCKU3P-L1SFVB784I4813 ?

 

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nmanitri
Xilinx Employee
Xilinx Employee
708 Views
Registered: ‎06-13-2018

Hi @Kaiyang ,

Bank 65 contains dedicated and dual-mode configuration pins. Tandem Configuration can use many of these pins, including the dedicated PCIe reset pin (PERSTN) in UltraScale+ devices, and many configuration pins, such as EMCCLK, CSI_B and address and data pins for wider interfaces.

 

The granularity of configuration in Xilinx devices is the height of a clock region, which matches the size of an IO bank.  In order to bring the PCIe reset pin (which by default is in Bank 65), then entire bank must be configure.  This means any user IO that must also go in this bank would come up with stage 1.  To make sure that you're clear that this will happen so you understand the potential behavior of IO with no logic yet driving it, we ask that you explicitly add these IO (and any other elements that fall into this configuration frame) to the stage 1 pblock.

Details, including constraint syntax, on how to do this is given in PG213.

https://www.xilinx.com/support/documentation/ip_documentation/pcie4_uscale_plus/v1_3/pg213-pcie4-ultrascale-plus.pdf#page=87

In general, we suggest that users avoid Bank 65 whenever possible, not only to avoid conflicts with Tandem Configuration, but to simply avoid the use of these special dual-purpose pins.  But if that is unavoidable, the identification of resources needed for stage1 will get you past these errors.

Note: Configuration Persist is required in Tandem PROM.

 

  1. For Tandem PCIe, the initial configuration requirements are no different than a standard configuration. Once DONE goes high after stage 1, those dual-mode IO are in user mode.

 

  1. For Tandem PROM, dual-mode configuration pins are persisted, so address bits, EMCCLK, etc. must remain in configuration mode so stage 2 can be loaded.  These cannot be user IO.

 

  1. If Field Updates are selected, bank 65 is in stage 1 which means nothing dynamic (like a MIG core) can use bank 65.  The update_region pblock cannot own bank 65.

 

Note that PERSTN in US+ can be moved, but the stage 1 IO pblock must move with it.

 

In the meanwhile, please check XAPP-883 and XAPP-1179 this will give you a better understanding.

As for the DDR4, does it require the use of bank 65 (or bank 64 if the reset pin must go there)?  If so, that's a conflict with the Tandem requirements. If you were just using Tandem PCIe, you could identify and assign any MIG core elements to these banks to have them come up in stage 1. The design must be separated by hierarchy as well.  We cannot have part of the MIG core in one hierarchy and the rest in another.  So the only possibility of meeting the hierarchy and floorplan requirements of Tandem, when a MIG core must use bank 65 is to have the entire MIG core in stage 1.  This means expanding the stage 1 pblock considerably as well as adjusting the design structure to keep these two parts of the design logically and physically separate.  In other words, we don't want users to put MIG cores over bank 65 because it leads to so many complications due to competing requirements.  We document this in PG213 but there's really no way to alert users in the tools until it is fully assembled.

 

If your goal is dynamic reconfiguration and not fast initial boot, then you should only consider DFX and not Tandem Configuration.  Tandem is specifically for the initial power-up of a device (or full reconfiguration) to meet 100ms enumeration; DFX is for on-the-fly reconfiguration of part of the device; Tandem with Field Updates is our pre-defined solution that combines these two functions. You might check the following link in case you want to use bank65 without enabling tandem

https://www.xilinx.com/support/documentation/application_notes/xapp1338-fast-partial-reconfiguration-pci-express.pdf

Regards,

Naveen

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11 Replies
nmanitri
Xilinx Employee
Xilinx Employee
709 Views
Registered: ‎06-13-2018

Hi @Kaiyang ,

Bank 65 contains dedicated and dual-mode configuration pins. Tandem Configuration can use many of these pins, including the dedicated PCIe reset pin (PERSTN) in UltraScale+ devices, and many configuration pins, such as EMCCLK, CSI_B and address and data pins for wider interfaces.

 

The granularity of configuration in Xilinx devices is the height of a clock region, which matches the size of an IO bank.  In order to bring the PCIe reset pin (which by default is in Bank 65), then entire bank must be configure.  This means any user IO that must also go in this bank would come up with stage 1.  To make sure that you're clear that this will happen so you understand the potential behavior of IO with no logic yet driving it, we ask that you explicitly add these IO (and any other elements that fall into this configuration frame) to the stage 1 pblock.

Details, including constraint syntax, on how to do this is given in PG213.

https://www.xilinx.com/support/documentation/ip_documentation/pcie4_uscale_plus/v1_3/pg213-pcie4-ultrascale-plus.pdf#page=87

In general, we suggest that users avoid Bank 65 whenever possible, not only to avoid conflicts with Tandem Configuration, but to simply avoid the use of these special dual-purpose pins.  But if that is unavoidable, the identification of resources needed for stage1 will get you past these errors.

Note: Configuration Persist is required in Tandem PROM.

 

  1. For Tandem PCIe, the initial configuration requirements are no different than a standard configuration. Once DONE goes high after stage 1, those dual-mode IO are in user mode.

 

  1. For Tandem PROM, dual-mode configuration pins are persisted, so address bits, EMCCLK, etc. must remain in configuration mode so stage 2 can be loaded.  These cannot be user IO.

 

  1. If Field Updates are selected, bank 65 is in stage 1 which means nothing dynamic (like a MIG core) can use bank 65.  The update_region pblock cannot own bank 65.

 

Note that PERSTN in US+ can be moved, but the stage 1 IO pblock must move with it.

 

In the meanwhile, please check XAPP-883 and XAPP-1179 this will give you a better understanding.

As for the DDR4, does it require the use of bank 65 (or bank 64 if the reset pin must go there)?  If so, that's a conflict with the Tandem requirements. If you were just using Tandem PCIe, you could identify and assign any MIG core elements to these banks to have them come up in stage 1. The design must be separated by hierarchy as well.  We cannot have part of the MIG core in one hierarchy and the rest in another.  So the only possibility of meeting the hierarchy and floorplan requirements of Tandem, when a MIG core must use bank 65 is to have the entire MIG core in stage 1.  This means expanding the stage 1 pblock considerably as well as adjusting the design structure to keep these two parts of the design logically and physically separate.  In other words, we don't want users to put MIG cores over bank 65 because it leads to so many complications due to competing requirements.  We document this in PG213 but there's really no way to alert users in the tools until it is fully assembled.

 

If your goal is dynamic reconfiguration and not fast initial boot, then you should only consider DFX and not Tandem Configuration.  Tandem is specifically for the initial power-up of a device (or full reconfiguration) to meet 100ms enumeration; DFX is for on-the-fly reconfiguration of part of the device; Tandem with Field Updates is our pre-defined solution that combines these two functions. You might check the following link in case you want to use bank65 without enabling tandem

https://www.xilinx.com/support/documentation/application_notes/xapp1338-fast-partial-reconfiguration-pci-express.pdf

Regards,

Naveen

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Kaiyang
Visitor
Visitor
647 Views
Registered: ‎06-06-2021

Hi nmanitri,

We use master SPIx4. We don't use EMCCLK. Can we move reset pin from bank65 to bank64? In that case,Bank 65 is still configured in stage 1? 

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nmanitri
Xilinx Employee
Xilinx Employee
628 Views
Registered: ‎06-13-2018

Hi @Kaiyang ,

I am assuming that you want to know that if we move reset pin pf DDR to bank64 will it work? Please correct me if my understanding is NOT correct.

As I mention in my previous reply that "when a MIG core must use bank 65 is to have the entire MIG core in stage 1.  This means expanding the stage 1 pblock considerably as well as adjusting the design structure to keep these two parts of the design logically and physically separate.  In other words, we don't want users to put MIG cores over bank 65 because it leads to so many complications due to competing requirements" If you are avoiding Bank 65 the stage2(application) will not conflict with Stage1.

Regards,

Naveen  

 

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nmanitri
Xilinx Employee
Xilinx Employee
572 Views
Registered: ‎06-13-2018

Hi @Kaiyang ,

Please let me know if you have any follow-up query related to this thread, else please close the thread by "Marking" the answer as an Accepted Solution.

Regards,

Naveen

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haitaox
Explorer
Explorer
445 Views
Registered: ‎04-13-2013

Hello nmanitri

If we do not use DDR4 on bank 65,but we want to use some gpio like led driver on bank 65,is it possible? Do we need to place all led driver logic on stage1?

Michael

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haitaox
Explorer
Explorer
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Registered: ‎04-13-2013

hello nmanitri, please check my question,thank you!

Michael

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nmanitri
Xilinx Employee
Xilinx Employee
394 Views
Registered: ‎06-13-2018

Hi @haitaox ,

Yes you can. Please watch below video for better understanding. 

https://www.youtube.com/watch?v=XVDwEfzrntA 

Regards,

Naveen 

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haitaox
Explorer
Explorer
390 Views
Registered: ‎04-13-2013

Thank you!

I am sorry I can not visit youtube for some special reason.Could you send me some document about it.

And Do we need to place all led driver logic on stage1?

Michael

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Thanks for god,I meet FPGA.
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nmanitri
Xilinx Employee
Xilinx Employee
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Registered: ‎06-13-2018
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Kaiyang
Visitor
Visitor
298 Views
Registered: ‎06-06-2021

Hi @nmanitri

As pictrue shown below,UltraScale plus support multiboot and fallback in stage1. Does UltraScale support this ? I didn't find any description from PG156 and PG195.

 

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nmanitri
Xilinx Employee
Xilinx Employee
271 Views
Registered: ‎06-13-2018

Hi @Kaiyang,

Yes, we support multiboot and fallback, but for fallback that’s only available for stage 1.

Regards,

Naveen 

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