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josephprodigy
Observer
Observer
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Registered: ‎08-05-2019

Kintex Ultrascale Plus Transciever Projects are Not Working

Hi,

We are using XCKU11P-3FFVE1517 in our new project. We are trying to implement PCIE protocol in the GTY Transceiver. When we started the project we found some different behavior from FPGA. Some of the bit file is programming, ILA core is coming and some other programs is getting programed but ILA core is not coming in the Vivado. Further investigation we found that D3 pin is completely Short. Short to GND and Short to VIO(3.3V). D3 is a clock capable pin IO_L7P_HDGC_AD5P_88. Thus we understood if the utilization of X3Y4 region is making some problem. When we utilize that region more than 50% then it is behavior is in a different manner. So is there is any method to not use the clock region which has the electrical connection from D3?

How we will route it in Vivado?

If i give not to use X3Y4 region fully then my project is not getting implemented in the Vivado?

Please help on this.

Thanks

Joseph George

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