05-13-2011 11:52 AM
Hi I'm using the PLBv46 core for EDK version 4.06a in a virtex-5 SX. If I understand correctly, this core wraps the endpoint block plus v1.13 core.
The endpoint block plus v1.13 core is suppose to support the lane polarity inversion. Will this mean that the EDK core will also support it?
Logically it should, but I don't want to make a mistake on my PCB.
05-17-2011 07:44 AM
You are correct that EDK essentially wraps the block plus core. PCI Express only has the receiver lane reverse, so the transmitter will not reverse. Only the receiver.
Hope this helps.
05-17-2011 02:03 PM
Let's say that I inverted my TX pair on the schematic. Can the root complex which my FPGA is connected to"re-invert" it? The TX pair from my FPGA will be connecte to the RX pair of the root complex.
05-17-2011 04:31 PM