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4,475 Views
Registered: ‎01-04-2011

Lane polarity inversion

Hi I'm using the PLBv46 core for EDK version 4.06a in a virtex-5 SX. If I understand correctly, this core wraps the endpoint block plus v1.13 core.

 

The endpoint block plus v1.13 core is suppose to support the lane polarity inversion. Will this mean that the EDK core will also support it?

 

Logically it should, but I don't want to make a mistake on my PCB.

 

Best regards

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3 Replies
luisb
Xilinx Employee
Xilinx Employee
4,465 Views
Registered: ‎04-06-2010

You are correct that EDK essentially wraps the block plus core.  PCI Express only has the receiver lane reverse, so the transmitter will not reverse.  Only the receiver.

 

Hope this helps.

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4,462 Views
Registered: ‎01-04-2011

Let's say that I inverted my TX pair on the schematic. Can the root complex which my FPGA  is connected to"re-invert" it? The TX pair from my FPGA will be connecte to the RX pair of the root complex.

 

Thanks

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luisb
Xilinx Employee
Xilinx Employee
4,458 Views
Registered: ‎04-06-2010

The root complex should be able to do this. In fact, most of them do this. You can always double check on your own by looking at the root port's datasheet.
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