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Visitor
Visitor
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Registered: ‎05-29-2018

MCDMA connection with PCIe

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I am tring to use MCDMA(Multi channel DMA) IP and PCIe interface in ZCU106 evaluation board.

 

At first time, I tried to use "DMA/Bridge Subsystem for PCIe, PG195", but, I need to change to the MCDMA.

But when I put a PCIe coponnent on block design in vivado, DMA/Bridge Subsystem is shown.

 

My question is this. Can I connect MCDMA with DMA/bridge subsystem with bridge mode?

How do I connect MCDMA with Bridge subsytem?

Is there any example?

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Moderator
Moderator
371 Views
Registered: ‎05-02-2017

hello @ace157 ,

 

When configured as a PCIe Bridge, received PCIe packets are converted to AXI traffic and received AXI traffic is converted to PCIe traffic. The
bridge functionality is ideal for AXI peripherals needing a quick and easy way to access a PCI Express subsystem. The bridge functionality can be used as either an Endpoint or as a Root Port. PCIe Bridge functionality is only supported for UltraScale+™ devices. and we have  AXI Multichannel Direct Memory Access (AXI MCDMA) IP provides high-bandwidthdirect memory access between the AXI4 memory mapped and AXI4-Stream IP interfaces. Its scatter gather capabilities also offload data movement tasks from the Central Processing Unit (CPU) in processor-based systems. Initialization, status, and management registers are accessed through an AXI4-Lite slave interface, may be we can try using both IP can be done 

 

 

Regards
Chandra sekhar
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1 Reply
Moderator
Moderator
372 Views
Registered: ‎05-02-2017

hello @ace157 ,

 

When configured as a PCIe Bridge, received PCIe packets are converted to AXI traffic and received AXI traffic is converted to PCIe traffic. The
bridge functionality is ideal for AXI peripherals needing a quick and easy way to access a PCI Express subsystem. The bridge functionality can be used as either an Endpoint or as a Root Port. PCIe Bridge functionality is only supported for UltraScale+™ devices. and we have  AXI Multichannel Direct Memory Access (AXI MCDMA) IP provides high-bandwidthdirect memory access between the AXI4 memory mapped and AXI4-Stream IP interfaces. Its scatter gather capabilities also offload data movement tasks from the Central Processing Unit (CPU) in processor-based systems. Initialization, status, and management registers are accessed through an AXI4-Lite slave interface, may be we can try using both IP can be done 

 

 

Regards
Chandra sekhar
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if solution provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

View solution in original post