03-30-2020 07:02 PM
I am tring to use MCDMA(Multi channel DMA) IP and PCIe interface in ZCU106 evaluation board.
At first time, I tried to use "DMA/Bridge Subsystem for PCIe, PG195", but, I need to change to the MCDMA.
But when I put a PCIe coponnent on block design in vivado, DMA/Bridge Subsystem is shown.
My question is this. Can I connect MCDMA with DMA/bridge subsystem with bridge mode?
How do I connect MCDMA with Bridge subsytem?
Is there any example?
04-01-2020 05:42 AM
hello @ace157 ,
When configured as a PCIe Bridge, received PCIe packets are converted to AXI traffic and received AXI traffic is converted to PCIe traffic. The
bridge functionality is ideal for AXI peripherals needing a quick and easy way to access a PCI Express subsystem. The bridge functionality can be used as either an Endpoint or as a Root Port. PCIe Bridge functionality is only supported for UltraScale+™ devices. and we have AXI Multichannel Direct Memory Access (AXI MCDMA) IP provides high-bandwidthdirect memory access between the AXI4 memory mapped and AXI4-Stream IP interfaces. Its scatter gather capabilities also offload data movement tasks from the Central Processing Unit (CPU) in processor-based systems. Initialization, status, and management registers are accessed through an AXI4-Lite slave interface, may be we can try using both IP can be done
04-01-2020 05:42 AM
hello @ace157 ,
When configured as a PCIe Bridge, received PCIe packets are converted to AXI traffic and received AXI traffic is converted to PCIe traffic. The
bridge functionality is ideal for AXI peripherals needing a quick and easy way to access a PCI Express subsystem. The bridge functionality can be used as either an Endpoint or as a Root Port. PCIe Bridge functionality is only supported for UltraScale+™ devices. and we have AXI Multichannel Direct Memory Access (AXI MCDMA) IP provides high-bandwidthdirect memory access between the AXI4 memory mapped and AXI4-Stream IP interfaces. Its scatter gather capabilities also offload data movement tasks from the Central Processing Unit (CPU) in processor-based systems. Initialization, status, and management registers are accessed through an AXI4-Lite slave interface, may be we can try using both IP can be done