cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Newbie
Newbie
4,265 Views
Registered: ‎10-10-2016

ML555 configuration problem

hello,

I am using the ML555 board with the xapp859 application.

I have tried the JTAG configuration mode of ML555, it works.

Then I tried the master SelectMAP mode, it doesn't work.

The mcs file have been programmed into the PROM and the headers have been set as the recommended setting.

I guess the problem is that I haven't programmed the CPLD mode.

So I want to know Where Can I find the CPLD(CoolRunner-2 XC2C32) image for ML555 board?   

 

 

 

 

the following picture is the configuration skematic of ML555.From it, I think the CPLD should be programmed to connect the flash and the fpga.

configuration skematic.jpg

 

 

 

 

 

thanks a lot for your help,

Minghui

0 Kudos
Reply
3 Replies
Newbie
Newbie
4,253 Views
Registered: ‎10-10-2016

I did google this problem and scan the ML555 UG. The UG says there is a default image programmed into the device to permit configuration for the virtex-5 FPGA.Maybe I have erased the CPLD.

So the last solution maybe is to write a CPLD image by hand :(

0 Kudos
Reply
Xilinx Employee
Xilinx Employee
4,236 Views
Registered: ‎08-01-2008

you can find all the documents here
http://www.xilinx.com/products/boards/ML555/docs.htm
Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.
0 Kudos
Reply
Visitor
Visitor
196 Views
Registered: ‎06-06-2019

The web page is invalid. Could you please provide a new url?

0 Kudos
Reply