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ndnsoulja
Participant
Participant
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Registered: ‎10-24-2018

New to PCIe, need some top level answers

Hi, as the title says, I'm starting my first PCIe project. I have some basic questions and hoping someone could be guide me to the correct path:

1. So, my OS(linux) will communicate to the FPGA(ultrascale+) via PCIe. What's all that i would need to make that happen? I'm reading about DMA IPs, PHY IPs, etc. do i need all these IPs? Is there any other IPs i'm missing

2. Does Xilinx provide everything needed to to make this communications happen?

3. I see there are PCIe solution vendors out there like Northwest Logic, PLDA, Xillybux, etc. what do these "soft block solutions" offer that is not provided from Xilinx?

 

I'm sure i'll have follow up questions, so thanks in advance to any help !

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evgenis1
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Registered: ‎12-03-2007

Hi @ndnsoulja , 

 

Answering your questions.

 

1. You'd need PCIe and DMA controller IP cores.

2. Yes

3. There is a number of 3'rd party vendors that develop soft PCIe cores to extend and customize features provided by Xilinx. Things like PCIe Gen4 support, which is not part of Ultrascale+ silicon. Or instantiating lots of PCIe endpoints, beyond what Ultrascale+ part provides hardened in silicon.

 

To build a simple PCIe+DMA system is fairly simple, and should take no more than 5 minutes of drag-and-dropping components in Vivado IPI, provided that you have some experience with that.

Quickly googling "xilinx pcie example design" turned up a couple of good links:

  https://forums.xilinx.com/t5/Design-Entry/Example-design-for-7-Series-PCIe-endpoint-and-DMA/td-p/812783

  https://www.xilinx.com/support/documentation-navigation/design-hubs/dh0084-pcie-tabbed-hub.html

 

 

Thanks,

Evgeni

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ndnsoulja
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Registered: ‎10-24-2018

Thanks @evgenis1 for the reply! I really appreciate the input as I'm starting down this new journey.

 

Regarding your point 3. What factors should I look into to determine if a 3rd party vendor would be better than using the Xilinx provided IPs? what are PCIe endpoints and how many are provided with Ultrascale+ part?

 

3. There is a number of 3'rd party vendors that develop soft PCIe cores to extend and customize features provided by Xilinx. Things like PCIe Gen4 support, which is not part of Ultrascale+ silicon. Or instantiating lots of PCIe endpoints, beyond what Ultrascale+ part provides hardened in silicon.

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evgenis1
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Registered: ‎12-03-2007

Hi @ndnsoulja , 

 

>> What factors should I look into to determine if a 3rd party vendor would be better than using the Xilinx provided IPs?

 

It depends on your product requirements. I'd say Xilinx PCIe IP core covers pretty much entire PCIe Gen1,2,and 3 spec, and should satisfy most of the typical requirements. Unless you need to have access to the source code and make customizations, or your board needs to have PCIe at specific transceiver location that silicon doesn't provide. 

 

 

>> what are PCIe endpoints and how many are provided with Ultrascale+ part?

 

It's between 2 and 6, and depends on the chip. How many, and specific locations are defined in PG213.

 

Thanks,

Evgeni

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