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Adventurer
Adventurer
8,466 Views
Registered: ‎01-28-2008

PC express device memory mapped II problem on Core i7

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Hi everyone,

 

I have developed a Epic interface using a Exiling MALLS device and also have developed a Linux kernel mode device driver for this. This system works well with older Core 2 Duo architecture machines. However, recently, I have plugged this interface board into a latest Intel Core i7 machine and now I am not able to see the memory mapped II registers. I have the following implementation for the memory mapped II region:

 

1.  Region 5: Memory at fcfff000 (32-bit, non-prefetchable) [size=512] ---> io registers

 

2. I used ioremap call to map the memory into the virtual memory interface.

 

Region 0: Memory at fcef0000 (64-bit, prefetchable) [size=64K]     --> io memory

 

I am able to write something and read that back from io memory region. 

 

Has anyone experience this behavior before? 

 

I appreciate any help or pointers to progress with this issue.

 

Thanks and regards,

 

Sanka

Message Edited by cesanka on 06-17-2009 01:34 AM
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Adventurer
Adventurer
9,873 Views
Registered: ‎01-28-2008

Hi Hermes,

 

I finally figured out the problem. It was a bug in my FPGA firmware code where I hadn't considered the difference in alignment of the two BARS. Once I have fixed this issue in the FW it works really well now. I believe the alignments on the BAR addresses varies among different architectures.

 

Hope this helps.

 

Regards,

 

Sanka

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Anonymous
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Hello,

 

Our system have the same problem.

We use ASUS P6TSE.

 

Best Regards, 

Hermes

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Adventurer
Adventurer
9,874 Views
Registered: ‎01-28-2008

Hi Hermes,

 

I finally figured out the problem. It was a bug in my FPGA firmware code where I hadn't considered the difference in alignment of the two BARS. Once I have fixed this issue in the FW it works really well now. I believe the alignments on the BAR addresses varies among different architectures.

 

Hope this helps.

 

Regards,

 

Sanka

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Anonymous
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Hello Sanka,

 

     This problem still confuses me. Could you describe more detail about your solution?

 

     My design is basic on XAPP1052, Bus Master DMA Reference Design, and I add more control registers in the system and only use BAR0.

If using Core 2 Quad 9400, the registers' values are correct when their address are between 0x80 and 0xFF;

however, if using Core i7 920, the registers' values are almost wrong when their address are between 0x80 and 0xFF.

 

    I look forward to your response.

 

Thank you,

Hermes

 
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Anonymous
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I am also using a Core i7, and cannot get the pio design to recognize the BARs. The configuration space stuff is all ok, but when I try and access a BAR, it says it cannot find any.
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Visitor
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Registered: ‎08-31-2010

I am seeing the same problem.  I can read/write correctly to address from 0x00 to 0x7F but it fails in address range 0x80 to 0xFF.  This repeats every 0x100.  The problem occurs when the board is connected to a PCIe gen2 slot which is connected to the north bridge.  When I move the board to another slot (Gen 1 connected to South Bridge) I can read/write correctly for the whole address range 0x00 to 0xFF.

 

Any ideas?

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Anonymous
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Hi wlhunterjr,

 

Maybe you could check "lower_addr" in UTS_64_TX_ENGINE.v.

 

Best regards,

Hermes

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Visitor
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Registered: ‎08-31-2010

When in slot2 and I read/write to address 0x180 sucessfully the lower address in the completion packet is 0x60.  When I move the card to slot3 and read/write to address 0x180 fails the lower address is also 0x60.  I can see the completion packets in both cases and they look almost identical except for the completion id and requestor id.

 

Thanks

Bill

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