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sebastianro
Participant
Participant
3,177 Views
Registered: ‎10-22-2010

PCI Express Transfer

Hi,

I read about the PCIe protocol, I read the Xilinx documentation about their
PCIe EP and I have a quesstion: I understand that the CPU, through the RC,
controls the transfer (issuing a read or write command) but how does the
processor know when to issue the read command? I mean if I have a memory,
on the EP side, that is updated every lets say 3 sec with new data how do I
read the new data: does the software on the CPU side have to make read
requests every 3 sec or does the EP signal an interrupt every time new data
is available, or...?

Thanks,
Sebastian
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1 Reply
luisb
Xilinx Employee
Xilinx Employee
3,168 Views
Registered: ‎04-06-2010

An interrupt sounds like a great solution to your problem.  You can send an interrupt upstream to have the root wake up and access the new data.  

 

There are probably other solutions, but this should be sufficient and is also not taking up much of your processor's time.