I read about the PCIe protocol, I read the Xilinx documentation about their
PCIe EP and I have a quesstion: I understand that the CPU, through the RC,
controls the transfer (issuing a read or write command) but how does the
processor know when to issue the read command? I mean if I have a memory,
on the EP side, that is updated every lets say 3 sec with new data how do I
read the new data: does the software on the CPU side have to make read
requests every 3 sec or does the EP signal an interrupt every time new data
is available, or...?