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Anonymous
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PCIE IP Hard macro in Vertex-5: 32bit word alignment on 64bit bus

Hi,

PCIE IP document does not mention anywhere about 32bit word alignment on 64bit bus. I'm wondering on which 32bit data lane of 64bit data bus my first data should when the address bit[2] is set to 1.

Is the IP taking care of putting the 32bit data on apropriate lane internally by looking at the header information?

Please guide me.

Thank you,
Dipak

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Observer
Observer
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Registered: ‎08-15-2007

If I understand your question correctly, then no, the core does not align your data, you have to do it yourself.  The TLP with data that you get will simply have the first DW in the first position for a data word.  You have to take care that it goes where it is intended.

f

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Visitor
Visitor
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Registered: ‎10-31-2009

PCI Express defines everything to be big endian, so I would expect the most significant 32 bits of the 64 bit word will be the first DWORD, and the least significant 32 bits will be second.

 

I am still working on my design, and have not verified that is correct yet. 

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