08-28-2018 10:12 PM
If I add DDR3(MIG with 2 controller) to the design then the alrady existing pcie(gen2 ,X4) core can not be detected by the Processor.DDR calib_complete is also coming high. Artix 7 FPGA is the development platform.I tried reboot,reset through command.if I remove 1 controller it is detecting randomly(eg:gen2 X1, gen1 X4,etc..). please help.
08-30-2018 02:10 PM
09-05-2018 03:01 AM
There is no failing constraints.all the timing constraints met.and iam using ISE 14.7 for designing it.
09-05-2018 07:37 AM
09-07-2018 11:33 PM
09-16-2018 11:09 PM
upto gen1 x4 it is detecting. if we go up further it is making issue.kindly tell some solution
09-17-2018 04:09 PM
09-19-2018 08:31 AM
09-19-2018 09:05 PM
I have roughly tried to capture this signals already.After Board power on LTSSM state came 16(L0 state).user lnk up status also was comming high. but whenever we try to boot the processor(using terminal access applications like putty)(processor will be initiating the PCIe),this state was gong to 2D(Timeout to detect), and user lnk status has gone low.clock lock status was coming high in both time
09-20-2018 02:20 AM
If i keep reset as '1', then the calib complete should come '0' right? but it is coming 1 agian
09-20-2018 10:55 AM
09-21-2018 12:34 AM
yes,With reset and without reset there is no impact.but i have noticed some other things.
1.in every compailation the Rxlane detection behaviour is different.
one time LTSSM state was in 00 and user reset was high and Rx status all are in 0 state
i just added PL_RECEIVER_HOT_RESET in chipscope and compailed. now the LTSSM state entered to 2D and user reset changed to 0. and Rx status now changed to 4,5,7 (detection failure),some times in 1 lane , some times in 2 lanes or 4 lanes also.
I have attached the Chipscope screen shots along with this replay.kidly check it
what we can conclude from this tests? noise coupling is happening if i add DDR3 in the design? can you tell any solution?
09-21-2018 07:09 AM
I am using Two DDR controllers.with one DDR it is getting detected, either of DDR3A or DDR3B(both I tried).
09-27-2018 03:25 PM
01-09-2019 09:32 PM
Sorry for the delayed reply.we have changed the oscillator for the pcie coz it won't support gen2_x4. but still the issue is not resolved.we have tried the above mentioned possibility. but there is only 10mV variation between with DDR and without DDR, that is also with in the tolerence and no noise coupling in these two conditions as well.there are differences in the MGTAVCC MGTAVTT dynamic current in the power report of these two deisgns. what could be the reason. i have attached the document with this reply. kindly look in to this and suggest any solution please.
01-10-2019 03:37 PM
With MGTAVCC, MGTAVTTT - the total peak-to-peak noise as measured at the input pin of the FPGA should not exceed 10 mVpk-pk. Please check page 228 of ug482.
When you say the following, it seems the noise is more than the requirement mentioned in the GT user guide and can you check the reason for the increase in the noise on MGT supplies when DDR is added to the design?
there is only 10mV variation between with DDR and without DDR