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Observer
Observer
470 Views
Registered: ‎03-20-2018

PCIe AXI Bridge 4.1 - M_AXI_B Transaction IDs

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I'm currently working with the DMA/Bridge Subsystem for PCI Express (in AXI Bridge mode).  I issue AXI transactions to my application over the M_AXI_B MM interface.  I'd like to issue AXI transactions with different IDs based on the address of the transaction.  What's the best way to achieve this behavior?

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Explorer
Explorer
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Registered: ‎08-14-2013

Re: PCIe AXI Bridge 4.1 - M_AXI_B Transaction IDs

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I believe the ID is generated internal to the core, and I don't think there is any way to control it.  Generally the ID should be considered an opaque value that only has meaning to the device that generated the ID in the first place.  AXI interconnect components will occasionally extend the ID value for routing purposes.  AXI slave devices must return it in responses without modification.  From the standpoint of an AXI slave, you cannot rely on the AXI ID field to have any particular value - some devices will fix it at zero, some will generate different IDs to keep track of parallel requests if they support reordering. 

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-16-2019

Re: PCIe AXI Bridge 4.1 - M_AXI_B Transaction IDs

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Hi,

Out of order data is controlled by ID of the transaction (AWID or ARID). Transactions carrying the same ID should come in the order they are generated, different IDs can come out of order.

Hope this helps!

Ebrahim

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Observer
Observer
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Registered: ‎03-20-2018

Re: PCIe AXI Bridge 4.1 - M_AXI_B Transaction IDs

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What in the PCIe Bridge controls the AXI transaction ID?

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Participant
Participant
354 Views
Registered: ‎10-24-2018

Re: PCIe AXI Bridge 4.1 - M_AXI_B Transaction IDs

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can you post a snapshot of your block diagram if you have one?
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Participant
Participant
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Registered: ‎10-24-2018

Re: PCIe AXI Bridge 4.1 - M_AXI_B Transaction IDs

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325 Views
Registered: ‎10-17-2019

Re: PCIe AXI Bridge 4.1 - M_AXI_B Transaction IDs

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Hello sir,

I am trying to write/read the register trhough AXI_LITE interface but i am not able to read it back that resgister. Could you please guide me how to write the registers through AXI_LITE interface.

I tried to write 0xbase_addrs+10h by 0xFFFFFFFF and then by using xill_printf i am trying to read it back but not getting rdata and rvalid .

you know to write on that register you can read BAR0 range. I kept microblaze interface with DMA/Bridge subsytem PCIe ip. So i am looking simulation only. In c have written like that

#include <stdio.h>
#include <sleep.h>
#include "platform.h"
#include "xil_printf.h"

#define pcie_ep_s_axi_lite 0x44A00010 //EP S_AXI_LITE M00
#define pcie_ep_s_axi_b 0x44A10000 //EP S_AXI_B

#define linkup_sig_baddr 0x44A20000 //Linkup signal

 

//#define pcie_conifg_addrs2 0x10000078

 


int main()
{
init_platform();

// print("Hello World\n\r");

/////////////////////////////////////////
unsigned int *pcie_ep_s_axi_lite_1 = (unsigned int *)pcie_ep_s_axi_lite;
// unsigned int *pcie_ep_s_axi_b_1 = (unsigned int *)pcie_ep_s_axi_b;
unsigned int *linkup_sig = (unsigned int *)linkup_sig_baddr;

// unsigned int *addr2 = (unsigned int *)bram_address2;
// unsigned int *trig_en = (unsigned int *)register0;
// unsigned int *rd_addr = (unsigned int *)register1;
// unsigned int *PS_DATA_READY = (unsigned int *)register2;
// int i, loop;
// int j = 8,n = 0;
//----------------------------------------------------------------------------------------

unsigned int pcie_ep_s_axi_lite_val = 0xFFFFFFFF;
// unsigned int pcie_ep_s_axi_b_val = 0xAABBCCDD;


// *trig_en = 0;
//----------------------------------------------------------------------------------------
//printf("\n*******Configuartion Pcie EP********\n");
// for(int k=0;k<7;k++)
// {
// for(i=0;i<64;i++)


if (*(linkup_sig)==1)
{
usleep(1);
*(pcie_ep_s_axi_lite_1) = pcie_ep_s_axi_lite_val; //
//
// *(pcie_ep_s_axi_b_1) = pcie_ep_s_axi_b_val; //

 

// printf("\t MATRIX A is %x and value is %x",(addr+i),*(addr+i));
usleep(10);
xil_printf("%x",*(pcie_ep_s_axi_lite_1));
usleep(1);
xil_printf("%x",(0x44A00000));
usleep(1);
xil_printf("%x",(0x44A00078));
usleep(1);
xil_printf("%x",(pcie_ep_s_axi_b));
// printf("%x",*(pcie_ep_s_axi_b_1));

 


}

 

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Explorer
Explorer
299 Views
Registered: ‎08-14-2013

Re: PCIe AXI Bridge 4.1 - M_AXI_B Transaction IDs

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I believe the ID is generated internal to the core, and I don't think there is any way to control it.  Generally the ID should be considered an opaque value that only has meaning to the device that generated the ID in the first place.  AXI interconnect components will occasionally extend the ID value for routing purposes.  AXI slave devices must return it in responses without modification.  From the standpoint of an AXI slave, you cannot rely on the AXI ID field to have any particular value - some devices will fix it at zero, some will generate different IDs to keep track of parallel requests if they support reordering. 

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Highlighted
285 Views
Registered: ‎10-17-2019

Re: PCIe AXI Bridge 4.1 - M_AXI_B Transaction IDs

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Thanks for reply.

Okay but in case ID vlue is zero so we should get rvalid signal high at zero value. and  ID is some value is there we set uring ip manual configuration setting. And i tried to read back the addresses from 00 offset to 24 offset for EP. But not getting rvalid high.

 

 

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