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dviz199
Observer
Observer
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Registered: ‎08-24-2018

PCIe Device Not Detected after Adding MIG

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Hello,

Might have a somewhat trivial problem here. Trying to enable DMA over PCIe. I first ran just DMA/Subsystem IP and was able to discover the device on the host PC. After adding in the MIG, the device is no longer discovered using "lspci". This led me to believe the problem is not in the xdma module (but I could be wrong).

I've tried playing with the input clock into the MIG since this post mentions that modifying the clock rate worked:

https://forums.xilinx.com/t5/PCIe-and-CPM/ZCU106-as-PCIe-endpoint-not-recognized-by-host-PC/td-p/887720

I changed the clock rate from 200MHz to 100MHz and Diff -> single ended. Just playing around with different clock configs and nothing has worked so far so decided it's time to reach out to the FPGA gods. 

This is my current block design:

dviz199_0-1616803200984.png

This MIG is on the bottom right, the xdma is on the top left. In the latest attempt, the clock is driven from a 100MHz clock through an IBUFDS. I can post close-ups on modules if needed.

Also, I'm using a ZC706.

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pvenugo
Moderator
Moderator
212 Views
Registered: ‎07-31-2012

@dviz199 ,

Looks like sys_rst_n of XDMA is the issue here and need to connect to BUFG ODIV.

 

Regards

Praveen


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pvenugo
Moderator
Moderator
213 Views
Registered: ‎07-31-2012

@dviz199 ,

Looks like sys_rst_n of XDMA is the issue here and need to connect to BUFG ODIV.

 

Regards

Praveen


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dviz199
Observer
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Registered: ‎08-24-2018

Hi @pvenugo, it seems your suggestion led me to the correct solution. This device is once again detected on the host pc. I'd enjoy learning how you were able to deduce that the problem was the reset with the limited information I provided.

Additionally, from this post: https://forums.xilinx.com/t5/Design-Entry/IPI-reset-net-not-allowed-to-be-connected-to-BUFG-IP/td-p/761501

I saw that "If you connect directly the external port in IPI, an IBUF will be automatically inferred during synthesis."

This led me to adding a "not" vector logic IP feeding from the external reset signal into the xdma rst_n port. Since, I was unable to generate a "BUFG ODIV" from IP (perhaps I was doing something wrong). In any case, the device is recognized which addresses the issue of this post. Thank you.