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Contributor
Contributor
482 Views
Registered: ‎08-22-2019

PCIe - Header of the TLP messages

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Hi,

I use Xilinx DMA Subsystem Bridge for PCIe IP core and the driver of this IP core. I know that PCIe messages are sent as TLP messages and I also know that the header is in the format below: 

ertfgsdfg.PNG

This format is for 32-bit addressing and taken from PCI Express® Base Specification Revision 3.0.

I know that this header is put together with data at Transaction Layer of PCIe. Thus, I have two questions:

1) Is this header created in a CPU/PC and sent to the Transaction Layer or Transaction Layer creates this header based on PCIe memory?

2) I know the length field is 1024 byte at most. But it is limited to 128 byte. Is the length value in the header is defined by PCIe memory or the driver? 

Thanks

 

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Adventurer
Adventurer
292 Views
Registered: ‎08-14-2013

Re: PCIe - Header of the TLP messages

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The descriptor format is detailed in table 5 on page 24.  The descriptors sit in host memory, not in registers on the FPGA.  The XDMA core will read the descriptors, interpret them, then tranfer the data according to the descriptors. 

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Adventurer
Adventurer
421 Views
Registered: ‎08-14-2013

Re: PCIe - Header of the TLP messages

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The TLPs will be created by the PCIe interface hardware - either the root complex converting a CPU memory read or write into a PCIe TLP, or a device DMA engine creating a TLP to perform a read or write against system memory.  Software never touches TLPs. 

The length field can have various limits.  The absolute max is 1024 DWORDS, or 4096 bytes.  Then there are two configurable parameters that sit in the PCIe configuration space of each device: max payload size and max read request size.  The max read request size determines the maximum length for read requests, and the max payload size determines the maximum length for everything else.  Each of these range from 128 to 4096 in power of two steps (128, 256, 512, 1024, 2048, 4096).  These settings are configured either by BIOS or by the operating system during boot.  Generally the max payload size is 128 or 256 bytes, while the max read request size is usually either 512 or 4096.  The length field of read and write requests is determined by whatever generates the TLP - it could be 1 or 2 DWORDS in the case of a CPU issued read or write, or much larger if issued by a DMA engine. 

Contributor
Contributor
404 Views
Registered: ‎08-22-2019

Re: PCIe - Header of the TLP messages

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Hi aforencich,

Thank you for the detailed answer.

When you say DMA engine, do you refer to dma engine in FPGA or Linux Kernel? I already use dma engine in FPGA - XDMA IP Core -. But I think I must use the DMA engine in Linux because it looks like Descriptor List of the DMA engine in FPGA is fixed to specific addresses. 

 

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Adventurer
Adventurer
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Registered: ‎08-14-2013

Re: PCIe - Header of the TLP messages

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That would be a DMA engine in a PCIe device, such as an instance of the XDMA IP core. 

Linux does not have a DMA engine, a DMA engine is a piece of hardware.  And it has been a very long time since computers have had separate DMA hardware. 

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Contributor
Contributor
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Registered: ‎08-22-2019

Re: PCIe - Header of the TLP messages

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So you say dma in the Xilinx IP core sets the length of the transfer based on the descriptor list which is sent by the CPU, at least this is what I understood. So, how do I ensure that multiple datawords of data is sent with a header rather than 1 or 2 DW?

Should I change the Descriptor List content of the xdma IP Core which is accessible with xdma driver on Windows?

https://www.xilinx.com/support/documentation/ip_documentation/xdma/v4_0/pg195-pcie-dma.pdf Capture.PNG

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Adventurer
Adventurer
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Registered: ‎08-14-2013

Re: PCIe - Header of the TLP messages

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Each descriptor has a source address, destination address, and length.  The length can be whatever you like, and the XDMA core will generate TLPs correspondingly, including segmenting the requested transfer across multiple TLPs and respecting 4K address boundaries as necessary. 

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Contributor
Contributor
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Registered: ‎08-22-2019

Re: PCIe - Header of the TLP messages

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Yes but the problem is  there is no length information in the Descriptor List memory blocks of the DMA/BridgeSubsystem for PCI Express.

The document:https://www.xilinx.com/support/documentation/ip_documentation/xdma/v4_1/pg195-pcie-dma.pdf

 

From page 67 to page 73, DMA Memory fields can be seen. The problem is there is no memory set for the length information. Maybe this IP core has a fixed length information and I should use two distinct IP cores, one for PCIe and one for DMA?

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Adventurer
Adventurer
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Registered: ‎08-14-2013

Re: PCIe - Header of the TLP messages

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The descriptor format is detailed in table 5 on page 24.  The descriptors sit in host memory, not in registers on the FPGA.  The XDMA core will read the descriptors, interpret them, then tranfer the data according to the descriptors. 

View solution in original post

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Contributor
Contributor
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Registered: ‎08-22-2019

Re: PCIe - Header of the TLP messages

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Thanks a lot for your help @aforencich 

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