03-05-2020 04:04 AM
Yes for End Point configuration, you can enable this option through a parameter DISABLE_LANE_REVERSAL that is set to a default value in the IP generated files, but I must stress this is not tested or supported.
If you do a search for DISABLE_LANE_REVERSAL in 7-Series generated files, you will see that the parameter is set to TRUE in the core_top.v file and is set to TRUE in pcie_7x and pcie_top files. Since the hierarchy of the files is in the following order core_top -> pcie_top -> pcie_7x, this would mean that the hard block does have support for lane reversal however the IP does not allow for this option. To do a lane reversal you will have to modify the DISABLE_LANE_REVERSAL parameter to FALSE in the core_top.v however as I stated this would not be a tested/supported configuration and I would not recommend it as we cannot confirm what behavior you will see and I would expect you may see problems with the link.
03-05-2020 04:20 AM
I forgot to mention the FPGA series. its ultrascale plus series (I think there is no importance for that).
What i did is, i have changed the DISABLE_LANE_REVERSAL bit in the files you have mentioned through a tcl script given by xilinx SR team.
The lane got reversed in Vivado. Before testing what i want to know is, does this harm the FPGA permanently?.
Unexpected behaviour for that corresponding bit file is ok fine.
Any one tested this?
03-05-2020 06:00 AM
This just a protocol thing and it should not damage the FPGA. But as I stated this is not tested and functionally it may not work from a PCIe protocol level when link training. Advise as per PG213 is that if the link partner has lane reversal enabled you should not enable this.
03-05-2020 07:14 AM
It is very difficult to identify whether the link partner (PC) have that capability enabled or not.
Any I'm gonna try this. Hope my PC dont have the lane reversal capability.