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Sig123456789
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Registered: ‎09-05-2020

PCIe PHY LTSSM query

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Hi

 

I am using PCIe PHY 1.0 IP for xczu9eg-ffvb1156 device on a custom board for developing a PCIe link on PL side. PCIe requirements are 2.5 GT/s and single lane. 

All the PCIe Base Specification guides tell me that there is an LTSSM state machine inside the PHY and PHY handle the initialization all by itself. But the PCIe PHY 1.0 ip document mention no such thing. All that is mentioned is that, in a tiny note, LTSSM should exist in MAC layer. Also is this ip example design project, a kind of small LTSSM is created in the test bench out side the IP.

Capture.PNG

 

So my straight forward question is that, while working with the PCIe PHY 1.0, do I have to implement the LTSSM state machine all by my self? Is my understanding correct? 

 

Thanks.

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feng.zhang
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Registered: ‎12-01-2019

Hi, Sig123456789.

 

Look at the fllowing picture.

 

PHYLayer.PNG

 

  • In my understanding, this PCIe PHY 1.0 IP is not the exact PCIe PHY block that is mentioned in all the PCIe Base Specification documents? 

PCIe PHY IP only implents PCS and PMA.

 

  • Elements like LTSSM, Scramble, De-scrambler, Tx/Rx Buffers and Byte stripping block are missing from this IP?

These functions you mentioned are implemented in MAC layer, not in this PHY IP. PIPE interface is used to connect MAC and this PHY IP.

 

  • PCIe PHY 1.0 IP does not mention any internal structure of the IP, such as its basic components. Where can I find the details about the components of this PHY IP? So that I can identify the missing components and design them in fabric.

If you want the know the details about PHY layer, you can read "PCI Express Base Specification".  I think it's not easy to implement the MAC layer on yourself, you'd better use the 3rd party MAC IP.

Likes @deepeshm said,  the most easy way is to use "DMA/Bridge Subsystem for PCI Express " or "GEN3 Integrated Blocks for PCI Express" IP in IP Catalog, then you no need to think the details of PCIe.

 

 

 

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deepeshm
Xilinx Employee
Xilinx Employee
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Registered: ‎08-06-2008

The PCI Express IP, in general, consists of two parts: PCIe PHY and PCIe MAC as shown in the figure below.

This block diagram is from https://www.xilinx.com/support/documentation/ip_documentation/pcie_phy_versal/v1_0/pg345-pcie-phy-versal.pdf

phy.PNG

The PHY IP that you are using is the one on the right side of the PIPE interface. If you want to use PCIe PHY and do the rest by yourself, you need to create the whole PCIe MAC part which is the part on the left of the PIPE interface shown above.

If you don't want to create anything on your own for PCIe as a whole, you should be looking at using the following IP:

https://www.xilinx.com/support/documentation/ip_documentation/pcie4_uscale_plus/v1_3/pg213-pcie4-ultrascale-plus.pdf

This comes with both PCIe PHY and PCIe MAC. The ltssm is handled within and you don't need to do anything.

Thanks.

Sig123456789
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Registered: ‎09-05-2020

I have been expecting you @deepeshm since I posted this question.

Thanks @deepeshm for the reply. Your answer has now cleared my doubts. But a new set of questions is also raised:

  • In my understanding, this PCIe PHY 1.0 IP is not the exact PCIe PHY block that is mentioned in all the PCIe Base Specification documents? 
  • Elements like LTSSM, Scramble, De-scrambler, Tx/Rx Buffers and Byte stripping block are missing from this IP?
  • PCIe PHY 1.0 IP does not mention any internal structure of the IP, such as its basic components. Where can I find the details about the components of this PHY IP? So that I can identify the missing components and design them in fabric.

Thanks

Sig

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feng.zhang
Participant
Participant
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Registered: ‎12-01-2019

Hi, Sig123456789.

 

Look at the fllowing picture.

 

PHYLayer.PNG

 

  • In my understanding, this PCIe PHY 1.0 IP is not the exact PCIe PHY block that is mentioned in all the PCIe Base Specification documents? 

PCIe PHY IP only implents PCS and PMA.

 

  • Elements like LTSSM, Scramble, De-scrambler, Tx/Rx Buffers and Byte stripping block are missing from this IP?

These functions you mentioned are implemented in MAC layer, not in this PHY IP. PIPE interface is used to connect MAC and this PHY IP.

 

  • PCIe PHY 1.0 IP does not mention any internal structure of the IP, such as its basic components. Where can I find the details about the components of this PHY IP? So that I can identify the missing components and design them in fabric.

If you want the know the details about PHY layer, you can read "PCI Express Base Specification".  I think it's not easy to implement the MAC layer on yourself, you'd better use the 3rd party MAC IP.

Likes @deepeshm said,  the most easy way is to use "DMA/Bridge Subsystem for PCI Express " or "GEN3 Integrated Blocks for PCI Express" IP in IP Catalog, then you no need to think the details of PCIe.

 

 

 

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Sig123456789
Visitor
Visitor
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Registered: ‎09-05-2020

Thanks @feng.zhang 

That very well answers all my queries. I am using xczu9eg-ffvb1156 device, that has no integrated block and that's why there is no DMA/Bridge subsystem available nor the integrated block.  On the other hand, I don't have the luxury to buy the 3rd party MAC IP.

So I am open to suggestion for some open source examples, in case you happen to know any.

Thanks for the help

 

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