01-28-2020 08:57 AM
I am entire noob to FPGA design, so please bear with me if this a stupid question to begin with.
I am looking to do the following design on ZCU102 development system with a XCZU9EG MPSoC, however, I am unsure if this is even possible with it:
1. PCIe PHY IP to provide MAC functionality
2. PCIe QDMA
An FMC daughter card will then be used to connect the GTH serdes to a PCIe cable interface.
I can select the part XCZU9EG in Vivado and Vivado allows me to add both IPs to the Design Sources. I then would like to use the example design for the QDMA which connects the AXI4 MM interface to the block RAM and the AXI4 Stream interface to a data generator which I thought would be convenient to begin with for testing. However on opening the example design Vivado responds with these error messages:
[IP_Flow 19-167] Failed to deliver one or more file(s).
[IP_Flow 19-3541] IP Elaboration error: Failed to generate IP 'qdma_0'. Failed to generate 'Elaborate Sub-Cores' outputs:
[Common 17-69] Command failed: Failed to generate IP 'qdma_0'. Failed to generate 'Elaborate Sub-Cores' outputs:
[Common 17-70] Application Exception: Failed to create subcore IP 'qdma_0_pcie4_ip'. The specified IP 'xilinx.com:ip:pcie4_uscale_plus:1.3' does not support the current part 'xczu9eg-ffvb1156-3-e'
Since the IP catalog allows adding the QDMA IP to the XCZU9EG I suppose the issue is related to the actual example design configuration. But beeing a noob I don't know how to overcome this.
I also don't understand quite yet how to connect two IPs to each other. In this case how do set up the design so that the PCIe PHY IP connects to the GTH transceivers on one side and then connects to the QDMA IP on the other side.
02-03-2020 08:39 AM
Which vivado version are you using?
QDMA IP has the PHY functionality in-built. It is not required to have PHY IP along with QDMAIP.
XCZU9EG MPSoC does not have PCIe hardblock primitives. This is the reason for the error you observed. QDMA IP also should not have been enabled in the IP catalog.
Can you use a different evaluation board for example VCU118?
02-03-2020 09:10 AM
Thank you for your response. Much appreciated.
> Which vivado version are you using?
Vivado HLx 2019.2.1
Vivado v2019.2.1 (64-bit)
SW Build: 2729669 on Thu Dec 5 04:48:12 MST 2019
IP Build: 2729494 on Thu Dec 5 07:38:25 MST 2019
> QDMA IP has the PHY functionality in-built. It is not required to have PHY IP along with QDMAIP.
Ok, I understand now. That was not clear to me.
> XCZU9EG MPSoC does not have PCIe hardblock primitives. This is the reason for the error you observed. QDMA IP also should not have been enabled in the IP catalog.
I read that somewhere but then I simply tried it in Vivado and it shows as available for the part. Please see screenshot attached. I don't have a license yet. I am supposed to get that from my client.
> Can you use a different evaluation board for example VCU118?
My client would like to use a MPSoC because they need the PS. Is there one that has the PCIe hardblock primitives? As a matter of fact, they want to have 2 QDMA endpoints. Is that possible?