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Participant sreevenkjan
Participant
1,153 Views
Registered: ‎03-12-2018

PCIe PIO Burst Mode

Hi Experts,

 

I am using the PCIe PIO testbench and I noticed that the Dataword(DW) size in Burst mode is limited to 30DW (30x32). I see that the root port requester is sending more than 30DW size packets however from the completer side there are no signals.

 

My question - is there a limitation on the completer side that it does not send more than 30DW? If there is no limitation how can I get more DW on the completer side?

 

Thanks,

SV

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8 Replies
Xilinx Employee
Xilinx Employee
1,125 Views
Registered: ‎08-02-2007

回复: PCIe PIO Burst Mode

Hi

The IP it could support more than 1DW or more than 30DW as payload

 there are two limitations

1 the PIO example only support 1DW

2 the MAX PAYLOAD Size set in the GUI and the MPS settings in the Root maybe below 128 byte

 

You will need to

1 change the PIO example to support more than 1dw

2 Change the default settings in GUI for MPS

3 Change the ROOT PORT top file and set the proper MPS

4 In the tx_usrapp.v file, change the MPS setting in the decive control register

 

change the value and set  the MPS you need (bit 7:5 is for MPS)

//Program PCIe Device Control Register

 

        TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG, 12'h68, 32'h0000005f, 4'h1);
        DEFAULT_TAG = DEFAULT_TAG + 1;
        TSK_TX_CLK_EAT(1000);

 

Defined encodings for this field are:
000b 128 bytes max payload size
001b 256 bytes max payload size
010b 512 bytes max payload size
011b 1024 bytes max payload size
100b 2048 bytes max payload size
101b 4096 bytes max payload size
110b Reserved
111b Reserved

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Participant sreevenkjan
Participant
1,106 Views
Registered: ‎03-12-2018

回复: PCIe PIO Burst Mode

Hi,

 

Yes I have changed the PIO example and it supports more than 1DW and it works until 256DW but however in simulation the Srq sends me signals only upto 30DW. I am using 64 bit memory mapped space.

 

I set the PCIe IP/GUI MPS settings as 1024bytes and also changed the tx_usrapp.v parameter "DEV_CAP_MAX_PAYLOAD_SUPPORTED" = 3 which should support MPS upto 1024bytes but still I get burst payload data upto 30DW. Do I need to change some parameter in the root port file?

 

How can I change the MPS setting in the device control register to below value?

 

TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG, 12'hC8, 32'h0000007f, 4'h1);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_CLK_EAT(1000);

 

Thanks,

SV

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Xilinx Employee
Xilinx Employee
1,070 Views
Registered: ‎08-02-2007

回复: PCIe PIO Burst Mode

Have you checked the MAX payload size in pcie3_uscale_rp_top.v and xilinx_pcie_uscale_rp.v file ?

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Participant sreevenkjan
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1,061 Views
Registered: ‎03-12-2018

回复: PCIe PIO Burst Mode

Hi,

 

I have assigned max payload size in those 2 files as 3'h3 which corresponds to 1024 bytes. My endpoint is also configured as 1024 bytes as Max Payload size. Also I have written the device control register value as below.

 

TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG, 12'hC8, 32'h0000007f, 4'h1);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_CLK_EAT(1000);

 

I have written data as 32'h0000007f because I want MPS to be 1024 bytes.Also when I do a data read after the TYPE0_config_write, I get back the following data (P_Read Data 32'h0000287f).

 

Am I writing the correct value in the type0_config_write?I cannot have a burst size greater than 32DW. What parameter do I need to change?

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Moderator
Moderator
1,016 Views
Registered: ‎02-16-2010

回复: PCIe PIO Burst Mode

Can you read device control register on Root Port to confirm it is also set to 1024bytes?

 

Example code from UltraScale+ IP example:
board.RP.cfg_usrapp.TSK_READ_CFG_DW(DEV_CTRL_REG_ADDR/4);
$display("[%t] : RP DEV CTL REG is %x", $realtime, board.RP.cfg_usrapp.cfg_mgmt_read_data);

 

In PG054, I find the device control register is at 0x68. If you are using Gen2 block in 7-series, please check table 2-23 of PG054.

Here is an example code to set EP device control register for 1024bytes. This example is for UltraScale+ device. So the register address could be different if you are using 7-series device.


// EP -- Program PCIe Device Control Register for max payload size == 1024 bytes

TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h78, 4'hF); //12'hC4
TSK_WAIT_FOR_READ_DATA;

TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG, 12'h78, (P_READ_DATA | (DEV_CAP_MAX_PAYLOAD_SUPPORTED * 32)) , 4'h1);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_CLK_EAT(1000);

TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h78, 4'hF); //12'hC4
TSK_WAIT_FOR_READ_DATA;
$display("[%t] : EP DEV CTRL REG Read data %x", $realtime, P_READ_DATA);

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Participant sreevenkjan
Participant
1,007 Views
Registered: ‎03-12-2018

回复: PCIe PIO Burst Mode

Hi Venkata,

 

Thanks for the reply, I use Virtex Ultrascale Gen3 Ultrascale PCIe IP. I have 2 questions.

 

In my case for CMPS (Check MPS) I get the below value.

 

TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'hC4, 4'hF);
TSK_WAIT_FOR_READ_DATA;

P_READDATA = 0x8003.

 

Q1 : I believe 2'h3 is for 1024 bytes right? Is the address 12'hC4 the correct address for device control register in Virtex Ultrascale? If not then can you point me where I can find this information in the xilinx product guide.

 

In the below code which you shared, can you tell me what the value of 

 

 

TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG, 12'h78, (P_READ_DATA | (DEV_CAP_MAX_PAYLOAD_SUPPORTED * 32)) , 4'h1);

 

Q2: What is the value of "DEV_CAP_MAX_PAYLOAD_SUPPORTED" in the above line?

 

regards,

SV

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Moderator
Moderator
1,000 Views
Registered: ‎02-16-2010

回复: PCIe PIO Burst Mode

For Virtex Ultrascale Gen3 Ultrascale PCIe IP, configuration space details are available in PG156. I find Device control register is at offset 0xC8.

pg156_device_control.JPG

 

As per Table 2-12, Table 2-17 of PG156,  2'h3 is for 1024 bytes of max payload size.

 

DEV_CAP_MAX_PAYLOAD_SUPPORTED is set to "3" in the test bench I referred to.

 

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Participant sreevenkjan
Participant
981 Views
Registered: ‎03-12-2018

回复: PCIe PIO Burst Mode

Hi Venkata,

 

The value when I read from device control register is 0x2810 and after I write the below command I get 0x2870. Is the value correct?

I am not still not able to get see data bigger than 30DW.

 

TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG, 12'hC8, (P_READ_DATA | (DEV_CAP_MAX_PAYLOAD_SUPPORTED * 32)),4'h1);

 

Yes you are right the 2'h3 is for 1024 bytes and I have assigned max payload size as 1024 bytes in my EP IP as well. My question is why do you write this data into device control register (P_READ_DATA | (DEV_CAP_MAX_PAYLOAD_SUPPORTED * 32)) ?

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