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damon84
Newbie
Newbie
3,412 Views
Registered: ‎07-11-2011

PCIe VHDL simulation with Active-HDL

I'm trying to get the Spartan 6 PCIe endpoint example simulated in Aldec Active-HDL (VHDL-only license), but I'm running into an issue with axi_basic_top - there seem to be only Verilog files for this portion of the project. Is it possible to simulate the Spartan 6 integrated block for PCIe within Aldec Active-HDL with only a VHDL simulation license? Thanks.

 

Damon

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jayer
Xilinx Employee
Xilinx Employee
3,399 Views
Registered: ‎08-07-2007

Hi,

 

If you use ISE 13.2 and generate a v2.3 S6 core, you will get VHDL files for the AXI wrapper source.

 

It will have to be able to simulate the underlying SecureIP model which requires a Verilog LRM-IEEE 1364-2005 encryption-compliant simulator The SecureIP models the GTPs and the PCIe block. I am not familiar with how Aldec would handle this but for a simulator like MTI, there is a way to enable this functionality without getting a full Verilog license.

 

Hope this helps,

John

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