I'm looking for FPGAs/SoCs which I can use for PCIe-Endpoints.
I need to support an isochronous data flow between the PCIe switch and the endpoints. As I understood so far, the switch requires to support the the following:
- Min. 2 Virtual channels VC)
- Time based weighted round robin (TBWRR)
My question: Do my PCIe endpoint also needs to support 2 VC's to support isochronous data flow?
The most of the FPGAs/SoCs i found only support 1 VC. Thus, I'm wondering if maybe 1 VC (@ the PCIe-Endpoint) is sufficient for isochronous data transfers and only the PCIe-switch needs to have 2 VCs?
Thanks in advance!