cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor
Visitor
4,173 Views
Registered: ‎02-16-2010

PCIe Xilinx device gets identified with precompiled bitstream but not with the one generated using the script file (PIO example)

Hello,

 

I am using AVNET ML509 board with Virtex 5  LX110T FPGA installed in a system with Linux Ubuntu 8.10 64-bit operating system. I wanted to get a start on using the PCIe and so have downloaded the reference design (PIO example) from http://www.xilinx.com/univ/xupv5-lx110t-refdes.htm  which uses the Endpoint Block plus core. I programmed the FPGA with the precompiled bitstream provided with the reference design. After warm reboot, the PC identified the Xilinx device (lspci). I then used the implement.sh script to generate the bitstream using Xilinx ISE 11.4 tools and programmed the FPGA with the same. I warm rebooted the system, but could not identify the device. The output of lspci has no Xilinx device i.e the device is not being identified. I am having the same problem with xapp1052 reference design. I do not understand why the device gets identified with the precompiled bitstream and not with the one generated using the script. Any help will be appreciated !

 

Thanks,

Sushrutha 

Tags (1)
0 Kudos
2 Replies
Highlighted
3,784 Views
Registered: ‎08-11-2010

Re: PCIe Xilinx device gets identified with precompiled bitstream but not with the one generated using the script file (PIO example)

Hi Sushrutha,

 

I am facing the same issue. I am using Avnet's LX110t eval board. After programming the FPGA with the bit stream, lspci does not identify the device. I am trying to use xapp1052 by the way. Could you please let me know if you found out what the problem is with this?

 

Thanks,

Chethan

0 Kudos
Highlighted
Visitor
Visitor
3,673 Views
Registered: ‎02-16-2010

Re: PCIe Xilinx device gets identified with precompiled bitstream but not with the one generated using the script file (PIO example)

Hello Chethan,

 

The ucf file generated by the core has incorrect pin locations for the clocks. Try using the correct pin LOCs.

 

These are the LOCs(incorrect) specified in the ucf that is generated with the core

 

#NET  "sys_clk_p"       LOC = "P4"  ;
#NET  "sys_clk_n"       LOC = "P3"  ;
#INST "refclk_ibuf"     DIFF_TERM = "TRUE" ;
NET  "sys_clk_p"       LOC = "AF4"  ;^M
NET  "sys_clk_n"       LOC = "AF3"  ;^M
INST "refclk_ibuf"     DIFF_TERM = "TRUE" ;

 

#NET  "sys_clk_p"       LOC = "P4"  ;

#NET  "sys_clk_n"       LOC = "P3"  ;

#INST "refclk_ibuf"     DIFF_TERM = "TRUE" ;

 

#NET "sys_reset_n"      LOC = "AE14"  | IOSTANDARD = LVCMOS25 | PULLUP | NODELAY ;

 

These are the correct LOCs.

NET "sys_reset_n"      LOC = "AC24"  | IOSTANDARD = LVCMOS25 | PULLUP | NODELAY ;

NET  "sys_clk_p"       LOC = "AF4"  ;

 

NET  "sys_clk_n"       LOC = "AF3"  ;

INST "refclk_ibuf"     DIFF_TERM = "TRUE";

 

Good Luck,

Sushrutha!

 

 

0 Kudos