PCIe config space read&write

[hayk.petr]

Dear Forum,

I am analyzing PCIE IP and need to understand its config signals.

The PCIe has many cfg_* signals which allows to make config space read&writes. In general all config signals are divided into following groups:

pcie2_cfg_err,interrupt/control/mgmt.

Could someone please explain how to make config read and write using these signals?

I want to read&write Status, Command registers of Config space.

thanks

Hayk

[hayk.petr]

Any updates?

[patocarr]

Hi,

  Which specific PCIe IP are you referring to? And also on what device?

Thanks,

-Pat

[hayk.petr]

Thanks for the reply.

I am using :xc7k70tfbg484-3

And the PCIe IP is: 7 Series Integreated Block for PCIE

( no DMA).

Thanks

Hayk

[patocarr]

Hi @hayk.petr 

  The cfg_mgmt interface is a generic read/write simple interface to access any register in the configuration space. Some of these registers are exposed as ports for simplicity, such as cfg_status, cfg_command, etc. See pg054 page 105 Designing with Configuration Space Registers and Configuration Interface for details on these ports.

  The interface is discussed on page 112-113, with read & write examples.

Thanks,

-Pat

[hayk.petr]

Hi @patocarr ,

Thanks much for the answer

What is difference between DRP interface and cfg_mgmt_* ports?

and what is "Internal Configuration Access Port Interface"- ICAP?

Thanks

Hayk

[patocarr]

Hi @hayk.petr 

  I haven't used the DRP interface but I understand it's used to change the IP configuration dynamically. The cfg_mgmt affects the runtime configuration of the core and reflects its status with its link partner.

  The ICAP is used in the MPSoC platform, from the Zynq side.

Thanks,

-Pat

[hayk.petr]

hi @patocarr ,

Thanks much.

When you say DRP interface is used to change the IP configuration dynamically, you mean after power on when Tandem mode PCIE is configured we can use DRP to modify some of PCIE config regs. Is my understanding right?

( During DRP mode as speck says the sys_reset should be assigned)

And for ICAP that means the ICAP ports are already connected to MPSoC and user cannot access them only Proc can access these ports. Right?

Thanks

Hayk

[hayk.petr]

Any updates please?

Thanks

Hayk

[hayk.petr]

Xilinx support?? Never heared about it.

[hayk.petr]

Any updates from Xilinx?