cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Adventurer
Adventurer
815 Views
Registered: ‎10-04-2018

PCIe config space read&write

Dear Forum,

 

I am analyzing PCIE IP and need to understand its config signals.

The PCIe has many cfg_* signals which allows to make config space read&writes. In general all config signals are divided into following groups:

pcie2_cfg_err,interrupt/control/mgmt.

 

Could someone please explain how to make config read and write using these signals?

I want to read&write Status, Command registers of Config space.

 

thanks

Hayk

0 Kudos
Reply
10 Replies
Adventurer
Adventurer
752 Views
Registered: ‎10-04-2018

Any updates?

0 Kudos
Reply
Teacher
Teacher
743 Views
Registered: ‎01-28-2008

Hi,

  Which specific PCIe IP are you referring to? And also on what device?

 

Thanks,

-Pat

 

Give kudos if helpful. Accept as solution if it solves your problem.
https://tuxengineering.com/blog

0 Kudos
Reply
Adventurer
Adventurer
679 Views
Registered: ‎10-04-2018

Thanks for the reply.

I am using :xc7k70tfbg484-3

 

And the PCIe IP is: 7 Series Integreated Block for PCIE

( no DMA).

 

Thanks

Hayk

 

0 Kudos
Reply
Teacher
Teacher
672 Views
Registered: ‎01-28-2008

Hi @hayk.petr 

  The cfg_mgmt interface is a generic read/write simple interface to access any register in the configuration space. Some of these registers are exposed as ports for simplicity, such as cfg_status, cfg_command, etc. See pg054 page 105 Designing with Configuration Space Registers and Configuration Interface for details on these ports.

  The interface is discussed on page 112-113, with read & write examples.

 

Thanks,

-Pat

 

Give kudos if helpful. Accept as solution if it solves your problem.
https://tuxengineering.com/blog

0 Kudos
Reply
Adventurer
Adventurer
620 Views
Registered: ‎10-04-2018

Hi @patocarr ,

Thanks much for the answer

 

What is difference between DRP interface and cfg_mgmt_* ports?

and what is "Internal Configuration Access Port Interface"- ICAP?

 

Thanks

Hayk

0 Kudos
Reply
Teacher
Teacher
609 Views
Registered: ‎01-28-2008

Hi @hayk.petr 

  I haven't used the DRP interface but I understand it's used to change the IP configuration dynamically. The cfg_mgmt affects the runtime configuration of the core and reflects its status with its link partner.

  The ICAP is used in the MPSoC platform, from the Zynq side.

Thanks,

-Pat

 

Give kudos if helpful. Accept as solution if it solves your problem.
https://tuxengineering.com/blog

0 Kudos
Reply
Adventurer
Adventurer
595 Views
Registered: ‎10-04-2018

hi @patocarr ,

Thanks much.

When you say DRP interface is used to change the IP configuration dynamically, you mean after power on when Tandem mode PCIE is configured we can use DRP to modify some of PCIE config regs. Is my understanding right?

( During DRP mode as speck says the sys_reset should be assigned)

And for ICAP that means the ICAP ports are already connected to MPSoC and user cannot access them only Proc can access these ports. Right?

 

Thanks

Hayk

0 Kudos
Reply
Adventurer
Adventurer
547 Views
Registered: ‎10-04-2018

Any updates please?

 

Thanks

Hayk

0 Kudos
Reply
Adventurer
Adventurer
387 Views
Registered: ‎10-04-2018

Xilinx support?? Never heared about it.

 

0 Kudos
Reply
Adventurer
Adventurer
264 Views
Registered: ‎10-04-2018

Any updates from Xilinx?

0 Kudos
Reply