12-02-2014 12:49 AM
Im trying to get the pcie gen3 example design to work, but i cant seem to implement it and see somthing with lspci.
If i use vivado (i prefer not to at this point) to create the example design then implement it and upload it to the fpga, i dont see anything when i use lspci. Whas i supposed to change something in the code or pin assignment?
I also tried to run the implement.sh script and upladed the routed.bit file created. still nothing on lspci.
If i try to use ise, i get this error:
ConstraintSystem:59 - costraint <NET "ext_clk.pipe_clock_i/CLK_TXOUTCLK" TNM_NET = "SYSCLK" ;> ... net not found...
What am i doing wrong? i want to see everything run on the fpga and to see it with lspci before i continue.
12-02-2014 12:52 AM - edited 12-02-2014 12:52 AM
Please check this link for discusison on similar error
12-02-2014 03:25 AM
You need to check the pin assign ments and GT locations to match with your board.
Regarding the warning of unable to find net, if this is your own design , then you need to check the hierarchy specified int he constraint.