11-03-2014 04:40 AM
When i do PCIe ipcore simulation, I connected the RP core and EP core through the PIPE interface. The PCIe ipcore of RP and EP uses 64bit address.When we transmite memory write TLP packet from RP to EP, it can be smoothly through the core. But when we transmite memory write TLP package from EP to RP, no packet can through, and RP/EP PCIe ipcore didn't report any error.
I dont know why?
It's very strange, when we transmite CPLD from EP to RP, the packet can smoothly through the core.
12-02-2014 04:20 AM
Can you give the specify contents of mem write Packet ?
Have you checked for Maxpayload size,4K address boundary limitations ?
12-17-2014 09:45 PM
Also check the bus master enable bit in the EP. This is also can be reason that often users miss to do .
You have to write a config write task to the config space of EP.