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wakingbefore
Observer
Observer
7,470 Views
Registered: ‎08-04-2014

PCIe ipcore for kintex 7(325T) Memory write cannot transmite from EP to RP.

Hi all:

       When i do PCIe ipcore simulation, I connected the RP core and  EP core through the PIPE interface.  The PCIe ipcore of RP and EP uses 64bit address.When we transmite memory write TLP packet from RP to EP, it can be smoothly through the core. But when we transmite memory write TLP package from EP to RP, no packet can through, and RP/EP PCIe ipcore didn't report any error.

       I dont know why?

       It's very strange, when we transmite CPLD from EP to RP, the packet can smoothly through the core.

       Have aynbody encountered this problem. Help me please!

 

 

 

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2 Replies
kotir
Scholar
Scholar
7,275 Views
Registered: ‎02-03-2010

Hi

 

Can you give the specify contents of mem write Packet ?

 

Have you checked for Maxpayload size,4K address boundary limitations ?

 

Regards,

KR

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kotir
Scholar
Scholar
7,151 Views
Registered: ‎02-03-2010

Hi

 

Also check the bus master enable bit in the EP. This is also can be reason that often users miss to do .

 

You have to write a config write task to the config space of EP.

 

Regards,

KR

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