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Registered: ‎09-05-2020

PCIe link starts retraining during PCIe Configuration/Enumeration

Please bear with me


I am writing a custom ip for pcie endpoint with Gen 2 and 4 Lanes. I have disabled the Scrambling/descrambling of pcie data (disable de-scramble/scramble is advertised in TS1 and TS2 ).

LTSSM states are entered in the following order:


After I reach L0 state and link training in Gen 2 with 4 Lanes is successful, the linkup goes high. There is a healthy exchange of flow control packets (init-FC1 followed by init-FC2 followed by a TLP message for power), which is normal. Then comes the configuration process where the root complex discovers the pcie device by sending and receiving CfgRd0 and CfgWr0 packets.


After I receive 8 configuration packets and send proper replies to those 8 packets, the linkup goes down. The reason is that, root complex leaves the L0 state and enter Recovery state (it sends EIEOS followed by TS1 etc...) and the link speed change bit in the TS1 is set high and Root complex is sending a speed change request from gen 2 to gen 1. I want to know why this behavior would occur?

Note: This issue is consistent.


  1. I want to know why this behavior would occur? is it normal? what should I do (move to gen 1???)?
  2. It always happens after the 8th configuration packet. All the TLPs are acknowledged with LCRC pass. So No LCRC issues there. Am I sending wrong contents in TLP packets? I guess not.. because I ran a complete simulation of my pcie ip with Xilinx root complex model and Configuration process completes, as normal, in the Vivado simulation.
  3. Disabling the Descrambling/Scrambling might has any thing to do with all this issue?
  4. Is it necessary to move to recovery state after L0?



Just to make sure that the pcie gen2 was not an issue. I gave up the idea of moving to gen 2 in the first place. So now I am only working with gen 1 and 4 lanes.

LTSSM states are entered in the following order:


After L0 I believe that I am done with the training and I have not written any code for any other state for saving time. 

The same issue appears, the root complex enter the recovery state, at gen 1 as well. No speed change this time.


Thanks in advance 







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1 Reply
Xilinx Employee
Xilinx Employee
Registered: ‎08-06-2008

Sounds like you have your own custom PCIe IP and this query is not related to Xilinx PCIe IP. 

I would suggest to check Xilinx PCIe IP link training stages and compare it to what you are seeing in your design. Perhaps that would help in debugging your issue. 

We are unable to comment on a custom PCIe IP implementation protocol issue.