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dave_pte
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Registered: ‎04-10-2019

PCIe on ZU48 works in verilog but not VHDL ?

If I use vivado 2020.2 to generate an example design for PCIe it generates a verilog top level, which is fine, but our company mandates the use of VHDL> I have therefore ported the top level (only so far) to VHDL. The verilog top level works just fine, but the VHDL one (they have identical sub components bt the way). Generates the following critical warnings and erros - am I missing something ? why are these errors related to the language used ?

  • [Vivado 12-2285] Cannot set LOC property of instance 'pcie_inst/inst/pcie4c_uscale_plus_0_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pcie4c_uscale_plus_0_gt_i/inst/gen_gtwizard_gtye4_top.pcie4c_uscale_plus_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[3].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST'... The pin direction of site GTYE4_CHANNEL_X0Y12 with package pin J38 does not match the given terminal pci_exp_rxp[7] ["d:/Onyx2/Onyx2.gen/pcie4c_uscale_plus_0/ip/pcie4c_uscale_plus_0/ip_0/synth/pcie4c_uscale_plus_0_gt.xdc":57]
  • [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks -of_objects [get_pins pcie4c_uscale_plus_0_i/inst/pcie4c_uscale_plus_0_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_userclk/O]]'. ["d:/pcie4c_uscale_plus_0_ex/imports/xilinx_pcie4_uscale_plus_x0y0.xdc":119]
  • [Vivado 12-5201] set_clock_groups: cannot set the clock group when only one non-empty group remains. ["d:/pcie4c_uscale_plus_0_ex/imports/xilinx_pcie4_uscale_plus_x0y0.xdc":119]
  • Place Design
  • [Place 30-1131] Cannot perform diagnostics because there is insufficient capacity to place all instances of type UNKNOWN_TYPE. This can be due to local capacity constraints imposed by user or clock region
  • [Place 30-68] Instance pcie_inst/inst/bufg_gt_sysclk (BUFG_GT) is not placed
  • [Place 30-1161] Could not place all instances for rule! Clock Rule: rule_bufds_gtychannel_intelligent_pin Rule Description: A BUFDS driving a GTYChannel must both be placed in the same or adjacent two clock regions (top/bottom) clkin (IBUFDS_GTE4.O) is locked to GTYE4_COMMON_X0Y4 pcie_inst/inst/pcie4c_uscale_plus_0_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pcie4c_uscale_plus_0_gt_i/inst/gen_gtwizard_gtye4_top.pcie4c_uscale_plus_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[3].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST (GTYE4_CHANNEL.GTREFCLK0) cannot be placed pcie_inst/inst/pcie4c_uscale_plus_0_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pcie4c_uscale_plus_0_gt_i/inst/gen_gtwizard_gtye4_top.pcie4c_uscale_plus_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[4].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST (GTYE4_CHANNEL.GTREFCLK0) cannot be placed pcie_inst/inst/pcie4c_uscale_plus_0_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pcie4c_uscale_plus_0_gt_i/inst/gen_gtwizard_gtye4_top.pcie4c_uscale_plus_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[3].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST (GTYE4_CHANNEL.GTREFCLK0) cannot be placed pcie_inst/inst/pcie4c_uscale_plus_0_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pcie4c_uscale_plus_0_gt_i/inst/gen_gtwizard_gtye4_top.pcie4c_uscale_plus_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[3].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST (GTYE4_CHANNEL.GTREFCLK0) cannot be placed pcie_inst/inst/pcie4c_uscale_plus_0_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pcie4c_uscale_plus_0_gt_i/inst/gen_gtwizard_gtye4_top.pcie4c_uscale_plus_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[3].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST (GTYE4_CHANNEL.GTREFCLK0) cannot be placed pcie_inst/inst/pcie4c_uscale_plus_0_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pcie4c_uscale_plus_0_gt_i/inst/gen_gtwizard_gtye4_top.pcie4c_uscale_plus_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[4].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST (GTYE4_CHANNEL.GTREFCLK0) cannot be placed pcie_inst/inst/pcie4c_uscale_plus_0_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pcie4c_uscale_plus_0_gt_i/inst/gen_gtwizard_gtye4_top.pcie4c_uscale_plus_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[4].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST (GTYE4_CHANNEL.GTREFCLK0) cannot be placed and pcie_inst/inst/pcie4c_uscale_plus_0_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/pcie4c_uscale_plus_0_gt_i/inst/gen_gtwizard_gtye4_top.pcie4c_uscale_plus_0_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[4].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST (GTYE4_CHANNEL.GTREFCLK0) cannot be placed
  • [Place 30-99] Placer failed with error: 'IO Clock Placer failed' Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
  • [Common 17-69] Command failed: Placer could not place all instances
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11 Replies
drjohnsmith
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Registered: ‎07-09-2009

dont change the top verilog,

   put a wrapper around it 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx11/ism_p_instantiating_verilog_module_mixedlang.htm

 

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dave_pte
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I can't do that, as I said, VHDL is mandated and I need to edit the application part, plus that doesn't help explain why the verilog version fails to place

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drjohnsmith
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Registered: ‎07-09-2009

I understand your "must use VHDL" 

    I've been involved in a good few projects on that side of things over the years since the Americans seem to have forgotten VHDL.

What I was suggesting was how I start ,

 

I do a wrapper around the verilog, 

    do NOTHING to the verilog , and prove that it builds / places and simulates.

Once I have that , I KNOW my ports are correct, and I have a simulation that will help us debug the conversion.

Only then do I start converting ,

     and a note , I don't always do it from the top down !

https://verilogguide.readthedocs.io/en/latest/verilog/vhdl.html

 

 

 

 

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richardhead
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Registered: ‎08-01-2012

If you "must do VHDL", then you're going to be coding alot of stuff Xilinx only provides in Verilog now, which is just about all of its cores.

If you're a VHDL engineer, you're going to have to learn to cope with mixed langauge designs or write your own.

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drjohnsmith
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Registered: ‎07-09-2009

Hi @richardhead

I get impresion that @dave_pte is in one of th eenviroments that the coding style / language is set form on high, and is not in a position to change it,

   What I understand they want to do, is to reverse engineer the Verilog to VHDL, 

       which we know is going to mean they are Verilog experts at the end, 

but for now, they want to start some where,

 

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dave_pte
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I already know Verilog extremely well and can cope with a mixed language environment just fine, but when you work for a company whose coding standard mandates the use of VHDL then there is no argument. To be clear however, they are not mandating that the IP has to be in VHDL, that would be impractical as you alluded to, however the design top level and any ancillary code (the PCIe companion app for example), MUST be in VHDL

richardhead
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Registered: ‎08-01-2012

Looking a bit more of the errors, I wonder if the path names are different with a vhdl wrapper around it. The best way to fix it is to open up the mapped or placed (but not routed) DCP and then use the constraint commands you have, then modify them until you can find the paths.

 

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drjohnsmith
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Registered: ‎07-09-2009

Just something to check,

  The other "silly" that has caught us out, is upper  v lower case , and the dreaded / or \ 

   

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dave_pte
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I absolutely take on board of eliminating possible situations, so I have done exactly what you sid. I have wrapped the top level verilog that itself synthesises and implements just fine into a component in a VHDL top level that only really passes to ports in/out to pins and now I get the same placement failures, so either it is a bug in vivado that can't route it when it's in VHDL or Richard's point about paths may be valid

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity top_level3 is
generic(
NUM_PCIE_LANES : integer := 8;
PCIE_AXI_WIDTH : integer := 256;
RQ_TUSER_WIDTH : integer := 62;
RC_TUSER_WIDTH : integer := 75;
CQ_TUSER_WIDTH : integer := 88;
CC_TUSER_WIDTH : integer := 33
);
port(
sys_clk_n : in std_logic;
sys_clk_p : in std_logic;
sys_rst_n : in std_logic;
pci_exp_txp : inout std_logic_vector(NUM_PCIE_LANES - 1 downto 0);
pci_exp_txn : inout std_logic_vector(NUM_PCIE_LANES - 1 downto 0);
pci_exp_rxp : inout std_logic_vector(NUM_PCIE_LANES - 1 downto 0);
pci_exp_rxn : inout std_logic_vector(NUM_PCIE_LANES - 1 downto 0)
);

end top_level3;

architecture rtl of top_level3 is

begin

pcie: entity xilinx_pcie4_uscale_ep
generic map(
PL_LINK_CAP_MAX_LINK_WIDTH => NUM_PCIE_LANES,
C_DATA_WIDTH => PCIE_AXI_WIDTH,
KEEP_WIDTH => PCIE_AXI_WIDTH / 8,
AXI4_CQ_TUSER_WIDTH => CQ_TUSER_WIDTH,
AXI4_CC_TUSER_WIDTH => CC_TUSER_WIDTH,
AXI4_RQ_TUSER_WIDTH => RQ_TUSER_WIDTH,
AXI4_RC_TUSER_WIDTH => RC_TUSER_WIDTH,
AXIS_CCIX_RX_TDATA_WIDTH => PCIE_AXI_WIDTH,
AXIS_CCIX_TX_TDATA_WIDTH => PCIE_AXI_WIDTH
)
port map(
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,

sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_rst_n => sys_rst_n
);

end rtl;

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drjohnsmith
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Registered: ‎07-09-2009

Your using 

pcie: entity xilinx_pcie4_uscale_ep
generic map(

 

How does the tool know where xilinx_pcie4_uscale_ep is 

you either need to define the component in your entity , or yo need to use the  .work format of declaration.

 

 

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richardhead
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Registered: ‎08-01-2012

@dave_pte 

We use many cores in our design that are VHDL wrappers around verilog without issue in vivado. If the source is verilog, then I highly recommend using a component rather than direct instantiation.