05-12-2021 08:48 AM
If I use vivado 2020.2 to generate an example design for PCIe it generates a verilog top level, which is fine, but our company mandates the use of VHDL> I have therefore ported the top level (only so far) to VHDL. The verilog top level works just fine, but the VHDL one (they have identical sub components bt the way). Generates the following critical warnings and erros - am I missing something ? why are these errors related to the language used ?
05-12-2021 10:12 AM
dont change the top verilog,
put a wrapper around it
05-12-2021 12:57 PM
I can't do that, as I said, VHDL is mandated and I need to edit the application part, plus that doesn't help explain why the verilog version fails to place
05-13-2021 02:29 AM
I understand your "must use VHDL"
I've been involved in a good few projects on that side of things over the years since the Americans seem to have forgotten VHDL.
What I was suggesting was how I start ,
I do a wrapper around the verilog,
do NOTHING to the verilog , and prove that it builds / places and simulates.
Once I have that , I KNOW my ports are correct, and I have a simulation that will help us debug the conversion.
Only then do I start converting ,
and a note , I don't always do it from the top down !
05-13-2021 05:52 AM
If you "must do VHDL", then you're going to be coding alot of stuff Xilinx only provides in Verilog now, which is just about all of its cores.
If you're a VHDL engineer, you're going to have to learn to cope with mixed langauge designs or write your own.
05-13-2021 06:53 AM
I get impresion that @dave_pte is in one of th eenviroments that the coding style / language is set form on high, and is not in a position to change it,
What I understand they want to do, is to reverse engineer the Verilog to VHDL,
which we know is going to mean they are Verilog experts at the end,
but for now, they want to start some where,
05-13-2021 08:10 AM
I already know Verilog extremely well and can cope with a mixed language environment just fine, but when you work for a company whose coding standard mandates the use of VHDL then there is no argument. To be clear however, they are not mandating that the IP has to be in VHDL, that would be impractical as you alluded to, however the design top level and any ancillary code (the PCIe companion app for example), MUST be in VHDL
05-13-2021 08:37 AM
Looking a bit more of the errors, I wonder if the path names are different with a vhdl wrapper around it. The best way to fix it is to open up the mapped or placed (but not routed) DCP and then use the constraint commands you have, then modify them until you can find the paths.
05-13-2021 09:00 AM
Just something to check,
The other "silly" that has caught us out, is upper v lower case , and the dreaded / or \
05-14-2021 12:59 AM
I absolutely take on board of eliminating possible situations, so I have done exactly what you sid. I have wrapped the top level verilog that itself synthesises and implements just fine into a component in a VHDL top level that only really passes to ports in/out to pins and now I get the same placement failures, so either it is a bug in vivado that can't route it when it's in VHDL or Richard's point about paths may be valid
entity top_level3 is
NUM_PCIE_LANES : integer := 8;
PCIE_AXI_WIDTH : integer := 256;
RQ_TUSER_WIDTH : integer := 62;
RC_TUSER_WIDTH : integer := 75;
CQ_TUSER_WIDTH : integer := 88;
CC_TUSER_WIDTH : integer := 33
sys_clk_n : in std_logic;
sys_clk_p : in std_logic;
sys_rst_n : in std_logic;
pci_exp_txp : inout std_logic_vector(NUM_PCIE_LANES - 1 downto 0);
pci_exp_txn : inout std_logic_vector(NUM_PCIE_LANES - 1 downto 0);
pci_exp_rxp : inout std_logic_vector(NUM_PCIE_LANES - 1 downto 0);
pci_exp_rxn : inout std_logic_vector(NUM_PCIE_LANES - 1 downto 0)
architecture rtl of top_level3 is
pcie: entity xilinx_pcie4_uscale_ep
PL_LINK_CAP_MAX_LINK_WIDTH => NUM_PCIE_LANES,
C_DATA_WIDTH => PCIE_AXI_WIDTH,
KEEP_WIDTH => PCIE_AXI_WIDTH / 8,
AXI4_CQ_TUSER_WIDTH => CQ_TUSER_WIDTH,
AXI4_CC_TUSER_WIDTH => CC_TUSER_WIDTH,
AXI4_RQ_TUSER_WIDTH => RQ_TUSER_WIDTH,
AXI4_RC_TUSER_WIDTH => RC_TUSER_WIDTH,
AXIS_CCIX_RX_TDATA_WIDTH => PCIE_AXI_WIDTH,
AXIS_CCIX_TX_TDATA_WIDTH => PCIE_AXI_WIDTH
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_rst_n => sys_rst_n
05-14-2021 01:34 AM
pcie: entity xilinx_pcie4_uscale_ep
How does the tool know where xilinx_pcie4_uscale_ep is
you either need to define the component in your entity , or yo need to use the .work format of declaration.
05-14-2021 01:55 AM
We use many cores in our design that are VHDL wrappers around verilog without issue in vivado. If the source is verilog, then I highly recommend using a component rather than direct instantiation.