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Visitor
Visitor
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Registered: ‎10-05-2017

PCIe reference clock on Artix 7

First a little background.  We are driving the PCIe bus on a Artix 7 XC7A50T-1FGG484I from an IMX7.  We currently have a 1 lane PCIe hooked up to: MGTREFCLK0N/P , MGTPRXP/N3, and MGTPTXP/N3.  With this configuration we see the PCIe reference clock coming from our source being pulled down (I believe).  With the FPGA PCIe interface totally disconnected from our source, the source reference clock looks as expected. 

 

My question is whats going on here?  I notice there are two input clocks on the FPGA MGTREFCLK0 and MGTREFCLK1: are we on the wrong clock pins?  Or is this simply a constraint or IP core setting that we have incorrect?  I can provide these files if that helps.

 

Thanks!

 

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Moderator
Moderator
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Registered: ‎02-16-2010

In figure A-4 of ug482 shows the REFCLK location constraints for FGG484 package in XC7A50T device. You can check if you set the GT location constraint correctly.
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Visitor
Visitor
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Registered: ‎10-05-2017

Can you elaborate a bit?  does it not matter which of the reference clocks we're wired to, that it can be set in the constraint?

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Visitor
Visitor
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Registered: ‎10-05-2017

Also my understanding is we had to youse TX/RX3 for our chip/package, but this figure shows all 4 four our chip/package?
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Moderator
Moderator
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Registered: ‎02-16-2010

The figure shows the available GT channels and refclk inputs. When you set a LOC constraint for GT channel (or) refclk input, those primitives will be used with your design.
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Visitor
Visitor
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Registered: ‎02-04-2018

The pcie ip lane only shows x0y0 if x1 option is chosen, but the vivado sets the clock lane to x0y4 after implementation.  Is there a way to change that implementation default?

I am running into this issue also, and ug482 is very vague.

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