10-19-2017 09:58 AM
First a little background. We are driving the PCIe bus on a Artix 7 XC7A50T-1FGG484I from an IMX7. We currently have a 1 lane PCIe hooked up to: MGTREFCLK0N/P , MGTPRXP/N3, and MGTPTXP/N3. With this configuration we see the PCIe reference clock coming from our source being pulled down (I believe). With the FPGA PCIe interface totally disconnected from our source, the source reference clock looks as expected.
My question is whats going on here? I notice there are two input clocks on the FPGA MGTREFCLK0 and MGTREFCLK1: are we on the wrong clock pins? Or is this simply a constraint or IP core setting that we have incorrect? I can provide these files if that helps.
10-19-2017 10:23 AM
10-19-2017 01:38 PM
02-06-2018 05:18 AM
The pcie ip lane only shows x0y0 if x1 option is chosen, but the vivado sets the clock lane to x0y4 after implementation. Is there a way to change that implementation default?
I am running into this issue also, and ug482 is very vague.