12-29-2011 11:34 PM
I would like to implement the PCIe Root Complex. My plan is to start with the CoreGen IP (from ISE13.3) and port to ML605.
But, my question is how to verify the design in hardware?
Can i test with just ML605 as root complex and ML507 as endpoint, using SMA cables to connect them, to test with a single DW transfer between them?
Also, if we want to test with the PCIe interface (not through SMA cable), is there any existing hardware board we can buy so that we can plug both ML605 and ML507 card on the board (something like motherboard) and test?
12-30-2011 01:25 AM
LeCroy offers a product called "PCI express DVT platform PXP-100a" which is from the former Catalyst company. I use it here for connecting the ML605 as root port to other PCIe cards. Basically this platform is a crosswired two-slot backplane with clock generator, reset logic and power-supply.
03-13-2012 08:29 PM
I would like to implement the PCIe Root Complex on ML605,too.
I'm going to buy the fmc card that you recommended above.
But how should I connect the xilinx pcie block ip to the HPC connector?
Especially, how should I deal with the GTX stuff? Do I have to modified the physical layer of the xilinx pcie ip?
Thanks a lot!
03-15-2012 07:08 PM
05-04-2012 04:34 AM
I got the FMC card this Monday and I successfully ran the example design(generated with the IP core) on 2 ML605 boards.
Thanks for your help :)