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Anonymous
Not applicable
10,954 Views

PCIe root complex implementation

I would like to implement the PCIe Root Complex. My plan is to start with the CoreGen IP (from ISE13.3) and port to ML605. 

 

But, my question is how to verify the design in hardware?

Can i test with just ML605 as root complex and ML507 as endpoint, using SMA cables to connect them, to test with a single DW transfer between them?

 

Also, if we want to test with the PCIe interface (not through SMA cable), is there any existing hardware board we can buy so that we can plug both ML605 and ML507 card on the board (something like motherboard) and test?

 

Thanks,

Ivan

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7 Replies
barco2
Adventurer
Adventurer
10,949 Views
Registered: ‎02-13-2009

LeCroy offers a product called "PCI express DVT platform PXP-100a" which is from the former Catalyst company. I use it here for connecting the ML605 as root port to other PCIe cards. Basically this platform is a crosswired two-slot backplane with clock generator, reset logic and power-supply.

 

Regards

Martin

luisb
Xilinx Employee
Xilinx Employee
10,937 Views
Registered: ‎04-06-2010

The FMC card below should work for you as well.

http://hitechglobal.com/FMCModules/FMC_PCIExpress.htm
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stancao
Visitor
Visitor
10,813 Views
Registered: ‎03-13-2012

Hi,luisb:

 

I would like to implement the PCIe Root Complex on ML605,too.

 

I'm going to buy the fmc card that you recommended above.

 

But how should I connect the xilinx pcie block ip to the HPC connector?

 

Especially, how should I deal with the GTX stuff? Do I have to modified the physical layer of the xilinx pcie ip?

 

Thanks a lot!

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luisb
Xilinx Employee
Xilinx Employee
10,781 Views
Registered: ‎04-06-2010

All you have to do is change the UCF with the correct location constraints. I have a UCF that should work. I'm on my cell phone right now, so I'll post the locations when I'm In the office tomorrow. If I don't, send me a message to remind me.
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stancao
Visitor
Visitor
10,762 Views
Registered: ‎03-13-2012

Hi,luisb:

 

Could you please send the UCF file you mentioned above to the following email:

 

stanc1987@gmail.com

 

Gratitude for your help:) 

 

Stan

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luisb
Xilinx Employee
Xilinx Employee
10,747 Views
Registered: ‎04-06-2010

Attached is a diagram showing you the connections for all devices

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stancao
Visitor
Visitor
10,695 Views
Registered: ‎03-13-2012

Hi,luisb:

 

I got the FMC card this Monday and I successfully ran the example design(generated with the IP core) on 2 ML605 boards.

 

Thanks for your help :)

 

Stan

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