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Adventurer
Adventurer
11,279 Views
Registered: ‎07-27-2011

PCIe root port will not except bus transfers larger than 128 bytes in simulation

I am running a  PCIe end port and  root port simulation using transfer sizes of 512 bytes and found that the transfers are limited to 128 bytes. I have set the root port  DEV_CAP_MAX_PAYLOAD_SUPPORTED = 5 which I think should allow 4096 byte transfers.  Also when building the end point core  I set the Max Payload Size  to 1024 bytes in the Device Capabilities Register  

Are there other parameters that are required for a larger packet size. 

 

Thanks 

 

John

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Moderator
Moderator
11,256 Views
Registered: ‎04-17-2011

Re: PCIe root port will not except bus transfers larger than 128 bytes in simulation

Moving to correct board - PCI
Regards,
Debraj
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Scholar
Scholar
11,246 Views
Registered: ‎02-03-2010

Re: PCIe root port will not except bus transfers larger than 128 bytes in simulation

Hi ,

 

The device advertises its MPS value through the Device Capability Register.

 

Once the system powers up, the root complex will evaluate the various MPS settings of the Device Capability Registers in the system. It will then write the MPS value the device must use into the Device Control Register.

 

Once set, the device must not generate TLPs with payload sizes larger than this value and must be able to accept TLPs with payload sizes up to this value.

 

 

Below is the answer record which would explain . Please have a look at it.

 

http://www.xilinx.com/support/answers/22880.htm

 

 

Regards,

Koti Reddy

 

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Adventurer
Adventurer
11,229 Views
Registered: ‎07-27-2011

Re: PCIe root port will not except bus transfers larger than 128 bytes in simulation

Hi Koti

 

The issue I am having is with the simulation environment. 

I have a root port for sim stimulus to the end port. 

The root port  DEV_CAP_MAX_PAYLOAD_SUPPORTED = 5 which I think should allow 4096 byte transfers

The end port  device capability reg reports 00008e03H, which I think allows 1024 byte transfers. 

When I run the simulation, only 128 byte transfers from the end port to the root port work.

All of the 256, 512 and 1024 byte transfers are not transferred to the root port.

 

Also when I build the end port core I find a Max of 1024 byte bursts are allowed, it this a limitation of the end port core?

 

 

Design environment = Vivado 2013.4  simulator 

device = Kintex 7 xc7k325tffg900-2

Target platform = KC705 

 

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Scholar
Scholar
11,203 Views
Registered: ‎02-03-2010

Re: PCIe root port will not except bus transfers larger than 128 bytes in simulation

Hi

 

Can you check the below signal ?

CFGDEVCONTROLMAXPAYLOAD[2:0]

 

DEV_CAP_MAX_PAYLOAD is one requested but need to be accpted by root port.

 

device control register is the value rootport sets. i believe this is set to 128 in your case.

If you want to increase further increase than th you have to follow the procedure as given below.

To program the device control register for the RP model, the following code needs to be added after system initialization.

      board.RP.cfg_usrapp.TSK_READ_CFG_DW(32'h32);
      board.RP.cfg_usrapp.TSK_WRITE_CFG_DW(32'h32, 32'h7f, 4'h1);
      board.RP.cfg_usrapp.TSK_READ_CFG_DW(32'h32);

 

 

Then the RP can use the TSK_TX_TYPE0_CONFIGURATION_WRITE task to write to the EP.

An example is given below.

      // increase MPS of the EP
      board.RP.tx_usrapp.TSK_TX_TYPE0_CONFIGURATION_WRITE(board.RP.tx_usrapp.DEFAULT_TAG, 32'h32, 32'h7f, 4'h1);

 

Basically this would put both the link partners to a common MPS value so the packet sizes would be the set to the desired values.

 

Regards,

KR

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