01-21-2019 07:29 AM
I'm trying to convert a Kintex Integrated Block PCIe v3.3 to a Ultrascale PCIev4.4 design.
The v3.3 only has 2 axi4 interface bus (m_axi and s_axi) but the v4.4 has 4 axi interface bus (m_axi_cq, s_axi_cc, m_axis_rc and s_axi_rq).
The PG156 is a little bit confusing using completer request and requester request and similar term which sounds very confusing and almost the same.
nI my case which are the two out of the four corresponding interface is the correct one to use if I need to match my original Integrated Block PCIe v3.3 design
01-29-2019 04:03 PM
We talk about 7-series to UltraScale IP Migration in PG156 starting on page 276: https://www.xilinx.com/support/documentation/ip_documentation/pcie3_ultrascale/v4_4/pg156-ultrascale-pcie-gen3.pdf#page=276
Let us know if you have any further questions.
02-11-2019 11:27 AM
The migration section of PG156 does cover most of the differences on the AXI bus.
It is a little bit confusing thought, hopefully someone could clarify.
7-series PCIe only has two bus, a master and slave axi bus where both the master and slave can initiate a write and read request. Also both the Master and slave bus can return a comnpletion packet.
Whereas the ultascale now has 4 axi bus, what I want to clarify is that, are the CQ and RQ is task with initiating r/w request.
What is confusing is the terminolgy usage of the Master and Slave. Seem .like in the Ultrascale, Master AXI-bus is refer to transmit and Slave AXI-bus refer to receiver whwereas in the 7-series, Master is refer to Link AXI-bus and Slave is refer to as the User side, is the correct?