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Newbie
Newbie
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Registered: ‎08-03-2020

PCIe v3.3 integrated block endpoint false path?

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target device: XC7A75 -3

IDE: Vivado 2018.1

PCIe core generated with Gen 2 speed and Enable Pipe Simulation switch on with AXIS clock = 125 MHz, AXIS data = 64bit

The failing path is between a FF (pclk_sel_reg) and the select input of a BUFGCTRL. The BUFGCTRL selects between a 250 MHz clock and a 125 MHz clock. The output of the BUFGCTRL provides the clock of the FF.

There are two failures for setup time, one for 125MHz to 250MHz clock and one for 250MHz to 250MHz.

My hunch is that this path should be constrained as a false path but I would like some confirmation since I am not certain about the BUFGCTRL requirements. 

 

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Newbie
Newbie
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Registered: ‎08-03-2020

Answered my own question by looking into the constraints generated with the example project. The paths to the select inputs of the BUFGCTRL should indeed be constrained as false-paths. 

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Highlighted
Newbie
Newbie
148 Views
Registered: ‎08-03-2020

Answered my own question by looking into the constraints generated with the example project. The paths to the select inputs of the BUFGCTRL should indeed be constrained as false-paths. 

View solution in original post

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