cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
6,557 Views
Registered: ‎01-28-2010

PCie Dsport not recoginze the bus master enabled Memory Read

HI xilinx Support,

 

 I used the Spartan 3 PCIe EP core. In this i have initiated Memory Read from the PIO design. The Dsport is not recoginze the Memory Read command. I have done the configuration write to enable the Core for bus master enable. Can any one tell me what is the problem. Is it xilinx Dsport support the Bus master enabled command? I am not receiving any information from the dsport. I used the Mem address is 0.

 

Can any one give me comments.

 

THanks & regards,

Aathinarayanan.C

0 Kudos
3 Replies
patocarr
Teacher
Teacher
6,481 Views
Registered: ‎01-28-2008

Hi AA,

 

  How can you tell the dsport doesn't recognize your non-posted request? Is it bouncing it back, or ignoring it? Do you see it going through to the trn_r* ports?

 

  Have you applied patch AR#33918? It patches to dsport to make it a 'root'.

 

HTH,

-Pat

 

Give kudos if helpful. Accept as solution if it solves your problem.
https://tuxengineering.com/blog

0 Kudos
genespar
Visitor
Visitor
5,722 Views
Registered: ‎11-04-2010

i have same problem, it just response "unsupported request" @cpl (Completion
Status Code)

0 Kudos
luisb
Xilinx Employee
Xilinx Employee
5,712 Views
Registered: ‎04-06-2010

a common reason a Completion with UR is sent is because of a BAR miss.  Have you verified that the address in your TLP is within a BAR's addressable range?

 

You can easily tell if you hit a BAR by looking at the TLP in ChipScope and verifying if the trn_rbar_hit_n asserts.

 

I've also seen BARs incorrectly configured when you constantly assert some of the cfg_* signals.  For instance, you don't want to tie  cfg_rd_wr_done_n low (asserted) forever.  Instead, you would want to tie this high(deasserted.)

0 Kudos