I am working on a Partial Reconfiguration Build and am running into some trouble. The logic that I am reconfiguring interfaces with an Axi4-Lite Bus, which is provided by the PCIe/DMA Bridge subsystem IP. So far I have been successful at loading the full bitstream over JTAG and have even been able to load the partial bitstream over JTAG. However, when I try to send the partial bitstream over the Xilinx PCIe driver, the driver seems to hang (or freeze). Any ideas?
Checking the validity of any AXI cores that are going to be affected. If you reconfigure a design, which reconfigures some AXI core on the bus, then there's a non-zero chance that an ongoing transaction would be lost. This would hang your system.
If you have to replace any AXI slave, consider using this firewall. It will guarantee valid upstream AXI transactions, even if the downstream core is unreliable. Asa bonus, if any slave doesn't respond properly (such as if it is in the middle of a reconfigure), the firewall will then reset the downstream core (as desired).