07-07-2009 01:27 AM - edited 07-07-2009 01:28 AM
I generated the pcie block plus v1.6 core, and implemented the example_design. Then I configured the V5 FPGA, and tried to access the memory space of the bar 1 using pcitree. But the system halted after several addresses had been visited.
Thank you for help!
07-09-2009 05:44 AM
The device that you are targeting, is it ES or the production device?
For PCIe block plus core after v1.5 you need production device.
The current core version is 11.1. You might want to try upgrading to a newer version.