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Visitor
Visitor
4,321 Views
Registered: ‎07-07-2009

Problem with the example_design

Hi,

 

I generated the pcie block plus v1.6 core, and implemented the example_design. Then I configured the V5 FPGA, and tried to access the memory space of the bar 1 using pcitree. But the system halted after several addresses had been visited. 

 

Thank you for help!

 

Message Edited by zuoyu on 07-07-2009 01:28 AM
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Xilinx Employee
Xilinx Employee
4,289 Views
Registered: ‎08-06-2008

The device that you are targeting, is it ES or the production device?

For PCIe block plus core after v1.5 you need production device.

The current core version is 11.1. You might want to try upgrading to a newer version.

 

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Xilinx Employee
Xilinx Employee
4,278 Views
Registered: ‎08-06-2008

Sorry the latest version is 1.11 not 11.1
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