cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Anonymous
Not applicable
8,059 Views

Problems connecting EP and RC

Jump to solution

Hi everyone,

 

First of all I want to explain that I am a newbie in PCIe communications.

 

I have created an PCIe EndPoint core and a PCIe RootPort core with core generator, as it is explained in the 

Virtex-6 FPGA Integrated Block for PCI Express User Guide document (UG517). I have simulated them, and they work fine (I have checked test ends with no failure). 

 

Then, my next step was connecting both cores, in order to stablish a PCIe communication between them. I have created a project similar to the one generated with both cores, with a top VHDL containing both cores, and connecting them in a similar way to the examples. When I simulate it, I have checked the signals and It doesn't work properly.

 

Below is the behaviour of the system:

 

- In the RootPort example, after the EndPoint configuration, It writes 3 words in 3 different memory positions, and then the RP reads them.

 

- In my RP-EP system, the EP is well configured. But when writing the first 3 words, the RP generates fine the trn_td signals, but the EP doesn't receive the three trn_rd wirte commands properly, only the third one. After that, when reading the memory, the data read obviously is not the desired one, and the state machine in PIO_CONTROLLER module abruptly stops (normal behaviour considering the data is not the expected one).

 

Does somebody know if I have to change something in one module or in both of them? Theoretically, they were suposed to be desgined to work together,but I can not make them work.

 

Thank you in advance,

 

Alberto.

0 Kudos
1 Solution

Accepted Solutions
Anonymous
Not applicable
13,849 Views

I have already solved my problem by tracing the signals through the whole system.

 

I have found out that EP and RP are not designed to work together just connecting them with cables. PIO_master application must be previously modified because the addresses are truncated in the EndPoint PIO application, so the addresses used in RootPort PIO master application are the same address for the EndPoint PIO application.

 

When modifying them, the system works great.

View solution in original post

0 Kudos
1 Reply
Anonymous
Not applicable
13,850 Views

I have already solved my problem by tracing the signals through the whole system.

 

I have found out that EP and RP are not designed to work together just connecting them with cables. PIO_master application must be previously modified because the addresses are truncated in the EndPoint PIO application, so the addresses used in RootPort PIO master application are the same address for the EndPoint PIO application.

 

When modifying them, the system works great.

View solution in original post

0 Kudos