05-21-2010 12:22 AM
I want to read/write the PCIe BARs using some logic (i mean some verilog/vhdl). Can any body help me with some related document/ application note or some sample code.
I am using virtex-5 lx50t device, ISE 11.4. I have generated the PCIe core using corgen but don't know how to proceed further.
Any type of help would be highly appreciated.
05-21-2010 08:05 PM
When you generate the core in Coregen there's a PIO example design provided as well.
There's also a testbench provided with the core that allows you to test out the functionality of the core.
There's a test called "pio_writeReadBack_test0" that will write to all the BARs of the core and reads the values back.
You can read about this in the User Guide and the Getting Started Guide:
02-03-2011 05:21 AM
I am using the sp605 board.
I want to integrate the pcie core.
I am following the simulation instructions provided by Xilinx but my simulation seems weird.
In the test environment I also do not have pio_writeReadBack_test0.
In simulation while debugging I am not able to get proper clocks i.e. trn_clk for tx data through the user logic.
My simulations I am running through is Modelsim.
Any feedback would be appreciated.
I would also like to know on the best practices to integrate the core / use the available core effectively with a custom design.
02-04-2011 04:08 PM
Can you also let us know what version of the core you're using? I don't believe all of the versions of the core have the pio_writeReadBack_test0. Only the latest version has it.