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efrath
Newbie
Newbie
965 Views
Registered: ‎09-27-2018

Receiving INTA irq from FPGA to the Root Complex

 

Hi all

Where can I read instructions regarding how to accept the irq coming from the Xilinx FPGA (as INTA through PCIe) ? as it is coming as "assert" and "dessert" messages and not as a physical line like most of the other devices.

The operating system is UBUNTU and the number of interrupts of our FPGA device are not inclining at :  /proc/interrupts .

our device is xc7vx690tffg1926-1 and we are using the "AXI Bridge for PCI Express Gen3" at the PCIe interface.

Thank you 

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kurihara
Xilinx Employee
Xilinx Employee
921 Views
Registered: ‎07-26-2012

If you are looking for a debugging guide, here is it;

AR#58495 ( https://www.xilinx.com/support/answers/58495.html )

 

 

 

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efrath
Newbie
Newbie
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Registered: ‎09-27-2018

Thank you but I'm familiar with this document 

I'm looking for more of a step guide of how to 'catch' the PCIe INTA irq on UBUNTU.

Our software guys can't see the irq on our Root Complex, maybe because it is arriving as a message and not a physical irq line 

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venkata
Moderator
Moderator
859 Views
Registered: ‎02-16-2010

Could you check the driver provided in AR#65444?
https://www.xilinx.com/support/answers/65444.html
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kurihara
Xilinx Employee
Xilinx Employee
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Registered: ‎07-26-2012

Is this problem occurring with the combination of the Add-in card on which the FPGA is mounted and the Linux PC?

If so, can you implement and test the Xilinx example design and related drivers?

AR#61444 (https://www.xilinx.com/support/answers/65444.html) describes the driver of DMA and how to use it. The DMA sends an interrupt signal at the end of the transfer. With PCIe IP, there is no special setting if you disable MSI when using Legacy interrupt.

 

I programmed XDMA on Xilinx evaluation board VC 709  and confirmed the reception of the interrupt just by inserting it into the linux machine incorporating the driver of AR # 61444 and ran it:

            CPU0       CPU1       CPU2       CPU3       CPU4       CPU5       CPU6       CPU7      
   0:         58          0          0          0          0          0          0          0   IO-APIC-edge      timer
   1:          3          0          0          0          0          0          0          0   IO-APIC-edge      i8042
   5:          0          0          0          0          0          0          0          0   IO-APIC-edge      parport0
   8:          1          0          0          0          0          0          0          0   IO-APIC-edge      rtc0
   9:          0          0          0          0          0          0          0          0   IO-APIC-fasteoi   acpi
  12:          4          0          0          0          0          0          0          0   IO-APIC-edge      i8042
  16:        491          0          0          0          0          0          0          0   IO-APIC   16-fasteoi   i801_smbus, xdma

===================================================================================

 

If possible, capture the cfg_interrupt_int and cfg_interrupt_sent signals with ila and check if the interrupt is sent from the FPGA. Also check in the command register that interrupt is not disabled.

 

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