Hello everyone! I'm trying to program fpga on sp605 with pcie example design (using ise 13.3) and face the problem. While sp605 with pcie example design inserted in PC slot - windows does not start. led_1 "user_reset" lights. If I add chip scope in the design using core output "user_clk_out" as clock signal, I see "slow or stopped clock" in it. Both signes mean that there is no clock signal on core outputs. I tried also to program fpga with GTP transceiver core only to check with chip scope if there any clock signals on its outputs, and it was ok. So it seems to me that there is some problem with example design. I tried two mother boards and situations was the same. Thank you!