Supported core pinouts - confusion

[assaf123]

Hi,

I have two questions:

1.

In UG341 it is writtenin table 5-3 that  for XC5VFX70T and lane X1,X2, the supported location for GTX is X0Y3, but in ML507 the location is actually X0Y2 and the design actually works.. how it is possible?

2.

In my costume board, I use XC5VFX30T. I didnt pay attention at the board design phase and connected the GTX transcievers for pcie in X0Y2, although it is written that to be supported only X0Y3. How and what should i change in the ucf file? maybe the blockrams locations? currently it was generated to be in X4Y0 X4Y1 X4Y2 X4Y3.

Should I and/or is it possible to use planahead to change the core locations? I am not shure what to do

Regards

[shuns]

Hi,

Regarding your questions:

1. That should be okay. The locations in the UG are only "supported" pinouts. You can still use other locations as long as the design meets timing.

2. Like point 1), it should be okay. You can just change your GTX LOC constriant in your UCF. If the final design meets timing, it should be fine.

-Yan Shun Li