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Registered: ‎03-10-2019

The method of full bandwidth of FPGA

         Pcie3.0 is implemented on kcu105, and the IP used is ultrascale gen3 integrated block. TLP protocol and DMA are implemented by RTL. There are some questions about the actual maximum bandwidth test of the PCIe.

         1. What method can be used to fill the bandwidth of the PCIe? My idea is to try to send MRD or MWR Package when tag and flow control have margin, wait for the host to return CPLD Package, and then calculate the actual bandwidth of the PCIe. However, this method is obviously unreliable.

         2. Is there a way to test the bandwidth of the PCIe by sending two MWR or MRD messages (not using up all the tags and traffic)?'

         3. Are there any related documents or exampples. 


     Thank you and look forward to your reply. Thanks!





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