i would like to translate the BMD Design to VHDL. Some statements are not clear to translate,can someone help me ?
Has anyone also translated the example design ?
This is basically just a big nested if-else statement. It happens to be at the declaration of the wire, but it could easily have been done elsewhere.
Below is an equivalent:
assign <output> = <condition> ? <input1> : <input0>;
if <condition> then
<output> <= <input1>;
<output> <= <input0>