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daryon
Adventurer
Adventurer
855 Views
Registered: ‎08-30-2018

Unable to grab PCIe ref_clk for the axi_pcie in ZC706 board !

Dear all,

 

I am working with Vivado 2017.2 targeting a ZC706 ZYNQ FPGA Board operating on an Ubuntu 16.4 Linux Machine.

 

Previously targeting a Kintex-7 KC705 Board, I was able to choose the PCIe_refclk as the input clock of the buffer in vivadoblock design and use it as the clock signal in my design. Indeed, by double-clicking on the Utility Buffer IP, I had the option to connect the CLK_IN_D pin of the buffer to the PCIe clock.

 

Recently, I have migrated to ZC706 which includes a XC7Z045FPGA. While this FPGa has the PCIe and GTx channel, I do not see the PCIe_ref_clk available in the board file (board options) and also the  lspci command in terminal does not ercognize the ZC706 board while it is connected to the motherboard's PCI bus and also the system was restarted!

 

I also verified these links (link1, link2, link3) and found nothing helpful !

Did anyone experience this problem before to help me to solve this issue?

 

Thanks,

Daryon,

1 Reply
bethe
Xilinx Employee
Xilinx Employee
651 Views
Registered: ‎12-10-2013

Hi @daryon,

 

Could you try the ZC706 example design of the PCIe core (XTP 246) or TRD ready-to-download, and see if one of those links up?   You should be able to create XTP246 in your desired Vivado version. 

 

From creating an example design, I see that the ZC706 PCIe block should be PCIe Block Location: X0Y0, and from the example design, the following constraints.  I would recommend creating the example design to get the rest of the needed user constraints, and an example of a top level wrapper or instantiation.

 

###############################################################################
# Pinout and Related I/O Constraints
###############################################################################

#
# SYS reset (input) signal.  The sys_reset_n signal should be
# obtained from the PCI Express interface if possible.  For
# slot based form factors, a system reset signal is usually
# present on the connector.  For cable based form factors, a
# system reset signal may not be available.  In this case, the
# system reset signal must be generated locally by some form of
# supervisory circuit.  You may change the IOSTANDARD and LOC
# to suit your requirements and VCCO voltage banking rules.
# Some 7 series devices do not have 3.3 V I/Os available.
# Therefore the appropriate level shift is required to operate
# with these devices that contain only 1.8 V banks.
#

set_property IOSTANDARD LVCMOS15 [get_ports sys_rst_n]
set_property LOC AK23 [get_ports sys_rst_n]
set_property PULLUP true [get_ports sys_rst_n]

###############################################################################
# Physical Constraints
###############################################################################
#
# SYS clock 100 MHz (input) signal. The sys_clk_p and sys_clk_n
# signals are the PCI Express reference clock. Virtex-7 GT
# Transceiver architecture requires the use of a dedicated clock
# resources (FPGA input pins) associated with each GT Transceiver.
# To use these pins an IBUFDS primitive (refclk_ibuf) is
# instantiated in user's design.
# Please refer to the Virtex-7 GT Transceiver User Guide
# (UG) for guidelines regarding clock resource selection.
#

set_property LOC IBUFDS_GTE2_X0Y7 [get_cells refclk_ibuf]

 

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