UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor mariom
Visitor
10,764 Views
Registered: ‎10-31-2013

Using DDR3 controller and PCI IP Core in Spartan 6

I need to implement an embedded system in an xc6slx45fgg484-2. The system contains one microblaze, one DDR3 controller and one PCI IP core and one CDMA but according the "place and route" tool the design is unrouteable (9983 signals are not completely routed).

 

The following message appears:

[Route 471]
This design is unrouteable. Router will not continue. To evaluate the problem please use fpga_editor. The nets listed below can not be routed:

 

If the DDR3 controller or the PCI IP core is removed from the system the "place and route" finishes successfully.

 

Any idea how to resolve this issue?

0 Kudos
6 Replies
Xilinx Employee
Xilinx Employee
10,763 Views
Registered: ‎07-11-2011

Re: Using DDR3 controller and PCI IP Core in Spartan 6

HI,

 

Please check if the constraints of MIG core were prpogating correctly.

Check if each of those IPs are implementing succeffully in standalone.

If you can share few of the unrouted paths we may have some more clues.

 

 

Regards,

Vanitha.

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented
0 Kudos
Visitor mariom
Visitor
10,729 Views
Registered: ‎10-31-2013

Re: Using DDR3 controller and PCI IP Core in Spartan 6

Hi Vanitha,

 

Thanks for attending this issue.

 

I was able to implement the DDR3 controller alone, but it was not possible to implement the PCI IP Core alone, there is the following warning:

 

1 signals are not completely routed.

WARNING:ParHelpers:360 - Design is not completely routed.

   system_i/plbv46_pci_0/plbv46_pci_0/PCI_CORE_S6_generate.pci_core_s6/XPCI_CORE/PCI_LC_I/OUT_CE/HARD_CE

 

any idea how to resolve it?

 

Regards,

 

Mario.

0 Kudos
Xilinx Employee
Xilinx Employee
10,721 Views
Registered: ‎07-11-2011

Re: Using DDR3 controller and PCI IP Core in Spartan 6

Hi,

 

Can you please share the IP, tool versions and core configuration files .xco ?

 

 

Regards,

Vanitha.

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented
0 Kudos
Visitor mariom
Visitor
10,711 Views
Registered: ‎10-31-2013

Re: Using DDR3 controller and PCI IP Core in Spartan 6

Hi,

 

The IP is the LogiCORE IP PLBV46 PCI Full Bridge (v1.04.a) and the software used is the PlanAhead 14.6.

 

Attached is the project that contains the IP mentioned above.

 

Please let me know  if you need more info.

 

Regards,

 

Mario

0 Kudos
Xilinx Employee
Xilinx Employee
10,677 Views
Registered: ‎07-11-2011

Re: Using DDR3 controller and PCI IP Core in Spartan 6

Hi,

 

Thanks for sharing the design, it looks like the path is very long and there are no placement constraints in the design so the tool facing dfficulty in PAR.

 

Can you recheck if the constraints got removed or not not generated properly ?

 

 

Regards,

Vanitha.

 

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented
0 Kudos
Visitor mariom
Visitor
10,657 Views
Registered: ‎10-31-2013

Re: Using DDR3 controller and PCI IP Core in Spartan 6

Hi,

 

I added some constrains (recommended by Xilinx) and re-implemented the design but the unrouted signal is yet present also there are some new warnings.

 

The attached file contains the project with the constrains file added.

 

Regards,

 

Mario.

0 Kudos