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Visitor
Visitor
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Registered: ‎12-15-2011

V7 Gen3 PCIe simulation hang in initial position

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Hi all

 

I try simulate IP for V7 Gen3 PCI Express. My options:

1) Virtex-7 vx690t

2) Core 'Virtex-7 FPGA Gen3 Integrated Block for PCI Express' v1.7 generated in ISE14.7

3) Core parameters - endpoint, x1, gen1, ref_clk 100Mhz. All other options default

4) Simulation instrument - ModelSim SE-64 10.2c

5) Start simulation by script simulate_mti.do

 

Program output finished with lines:

# Running test {pio_writeReadBack_test0}......
# [ 0] : System Reset Is Asserted...
# [ 4995000] : System Reset Is De-asserted...

 

After this I simulating more than 1ms, but nothing else happens.

Core outputs cfg_ltssm_statecfg_phy_link_status always 0. sys_clk look well, on EP/pci_exp_rxn/rxp I see some activity.

 

Some ideas?

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Visitor
Visitor
13,964 Views
Registered: ‎12-15-2011

Re: V7 Gen3 PCIe simulation hang in initial position

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I'm sorry, I find my error. By default core top level wrapper included in EP module without parameters transfer. It led to different PL_LINK_CAP_MAX_LINK_WIDTH value between modules, and pci_exp_rxn/rxp not connect from top module to core.

View solution in original post

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Highlighted
Visitor
Visitor
13,965 Views
Registered: ‎12-15-2011

Re: V7 Gen3 PCIe simulation hang in initial position

Jump to solution
I'm sorry, I find my error. By default core top level wrapper included in EP module without parameters transfer. It led to different PL_LINK_CAP_MAX_LINK_WIDTH value between modules, and pci_exp_rxn/rxp not connect from top module to core.

View solution in original post

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